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INTEGRATED CIRCUITS
DATA SHEET
PCF50732 Baseband and audio interface for GSM
Objective specification File under Integrated Circuits, IC17 1999 May 03
Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
CONTENTS 1 2 3 4 5 6 7 8 8.1 8.2 9 9.1 9.2 9.3 10 10.1 10.2 10.3 11 11.1 11.2 11.3 11.4 12 12.1 12.2 12.3 13 13.1 13.2 13.3 13.4 FEATURES APPLICATIONS GENERAL DESCRIPTION ORDERING INFORMATION QUICK REFERENCE DATA BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION General Baseband and voice band reference voltages BASEBAND CODEC Baseband transmit path Baseband receive path Baseband Serial Interface (BSI) VOICE BAND CODEC Voice band receive path Voice band transmit path Voice band digital circuitry AUXILIARY FUNCTIONS Automatic Gain Control (AGC): AUXDAC1 Automatic Frequency Control (AFC): AUXDAC2 Power ramping: AUXDAC3 Auxiliary analog-to-digital converter (AUXADC) CONTROL SERIAL INTERFACE (CSI) The serial interface Control Serial Interface (CSI) timing characteristics Control register block VOICE BAND SIGNAL PROCESSOR (VSP) Hardware description VSP assembler language Descriptions of the VSP instruction set The assembler/emulator 14 15 16 17 18 18.1 18.2 18.3 18.4 18.5 18.6 LIMITING VALUES
PCF50732
THERMAL CHARACTERISTICS DC CHARACTERISTICS AC CHARACTERISTICS FUNCTIONAL CHARACTERISTICS Baseband transmit (BSI to TXI/Q) Baseband receive (RXI/Q to BSI) Voice band transmit (microphone to ASI) Voice band receive (ASI to earphone) Auxiliary digital-to-analog converters Auxiliary analog-to-digital converters: AUXADC1, AUXADC2, AUXADC3 and AUXADC4 Typical total current consumption Typical output loads APPLICATION INFORMATION Wake-up procedure from Sleep mode Microphone input connection and test set-up PACKAGE OUTLINES SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DEFINITIONS LIFE SUPPORT APPLICATIONS
18.7 18.8 19 19.1 19.2 20 21 21.1 21.2 21.3 21.4 21.5 22 23
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Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
1 FEATURES
PCF50732
* Low power and low voltage device in 0.25 micron CMOS technology; supply voltage: analog 2.7 V (typical) and digital 1.5 V (typical) * Compatible with GSM phase 2 and DCS1800 recommendations * Complete in-phase and quadrature component interface paths between the Digital Signal Processor (DSP) and RF circuitry * Complete linear PCM CODEC for audio signal conversion between earphone/microphone and DSP * Four auxiliary analog inputs for measurement purposes (e.g. battery monitoring) * Three auxiliary analog outputs for control purposes (i.e. AFC, AGC and power ramping control) * Separate baseband, audio and control serial interfaces * Voice band Signal Processor (VSP) for flexible audio data processing. 2 APPLICATIONS
* The digital Baseband Serial Interface (BSI), which exchanges baseband data between the PCF50732 and the digital signal processor. The interface also includes signals to power-up and power-down the baseband transmit (TX) and receive (RX) paths. The voice band CODEC is a complete analog front-end circuit. It consists of four parts: * The receive path, which converts a digital signal to an analog signal for an earpiece, an external loudspeaker or a buzzer * The transmit path, which receives the analog external signal from a microphone and converts it into a digital signal * The Voice band Signal Processor (VSP), which filters the voice band data * The digital Audio Serial Interface (ASI), which connects the digital linear PCM signals of the receive and transmit paths to an external DSP. The voice band data is coded in 16-bit linear PCM twos complement words. The auxiliary Analog-to-Digital Converter (ADC) section consists of four input channels specified for battery management applications. The auxiliary Digital-to-Analog Converter (DAC) section consists of three DACs for Automatic Gain Control (AGC), for Automatic Frequency Control (AFC) and for power ramping. The Control Serial Interface (CSI) is used to program a set of control registers, to store the power amplifier ramping characteristics into the dedicated RAM and to transmit auxiliary ADC values to the DSP. It also controls switches, modes and power status of the different parts of the IC.
The CMOS integrated circuit PCF50732, Baseband and audio interface for GSM, is dedicated to wireless telephone handsets conforming to the GSM recommendations phases 1 and 2, DCS1800 and PCS1900. 3 GENERAL DESCRIPTION
The baseband CODEC is a complete interface circuit between the RF part in a mobile communication handset and the Digital Signal Processor (DSP). It consists of three parts: * The receive path, which transforms the quadrature signals from the RF (I/Q) to digital signals * The transmit path, which transforms a bitstream to analog quadrature signals for the RF devices 4 ORDERING INFORMATION
PACKAGE TYPE NUMBER NAME PCF50732H LQFP48 DESCRIPTION plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm VERSION SOT313-2
1999 May 03
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Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
5 QUICK REFERENCE DATA PARAMETER digital supply voltage analog supply voltage analog supply current average power consumption total standby current master clock frequency operating ambient temperature VDDA VDDD VDDD = 1.5 V; VDDA = 2.7 V; RXON active VDDD = 1.5 V; VDDA = 2.7 V; note 1 CONDITIONS MIN. 1.0 2.5 - - - - -40 TYP. 1.5 2.7 3.5 15 10 13.0 +27
PCF50732
SYMBOL VDDD VDDA IDDA Pav Istb(tot) fclk Tamb Note
MAX. 2.75 2.75 - - - - +85
UNIT V V mA mW A MHz C
1. Without load on audio outputs EARP, EARN, AUXSP and BUZ.
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Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
6 BLOCK DIAGRAM
PCF50732
handbook, full pagewidth
VDDD 7
VDDA(bb) 25
VDDA(vb) 37
VDDA(vbo) VDDA(ref) 47 34 REFERENCE VOLTAGES AND CURRENTS 36 Vref
PCF50732
10 TXON BIEN 19 16 GMSK MODULATOR 10 15 17 BSI
10-BIT DAC
LP
10-BIT DAC
LP 23
BIOCLK BDIO
QP QN IP IN AUXADC1 AUXADC2 AUXADC3 AUXADC4
ADC 20 18 DIGITAL FILTER ADC 2 M U X
24 21 22 27 28 29 30
RXON BOEN
AUXST CCLK CEN CDI CDO AMPCTRL
13 9 10 11 12 14 8 CSI DAC3 CTL 64 x 10-BIT SRAM 10 AUXDAC3 10-BIT AUXDAC2 12-BIT AUXDAC1 8-BIT 2 M U X 33
AUXDAC3
12
32
AUXDAC2
31 40 41 38 39 46
AUXDAC1 MICP MICN AUXMICP AUXMICN EARP EARN
ACLK AFS ADI ADO
4 3 2 1 ASI
VOICE BAND SIGNAL PROCESSOR
DECIMATION FILTER
MICADC
IRAM
NOISE SHAPER
EARDAC 1 MHz
OUTPUT AMPLIFIER
45
MCLK
6
CLOCK GENERATOR
OUTPUT AMPLIFIER
44
AUXSP
RESET
5 8 VSSD 26 VSSA(bb) 42 48 35
OUTPUT AMPLIFIER
43
BUZ
MGR988
VSSA(vb) VSSA(vbo) VSSA(ref)
Fig.1 Block diagram.
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Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
7 PINNING PIN SYMBOL ADO ADI AFS ACLK RESET MCLK VDDD VSSD CCLK CEN CDI CDO AUXST AMPCTRL BIOCLK BIEN BDIO BOEN TXON RXON IP IN QP QN VDDA(bb) VSSA(bb) AUXADC1 AUXADC2 AUXADC3 AUXADC4 AUXDAC1 AUXDAC2 NR. TYPE(1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 O/TS I I I I I P G I I I O/TS I O O/TS O I/O O I I I/O I/O I/O I/O P G I I I I O O ACTIVE LEVEL - - - - LOW - - - - LOW - - HIGH - - LOW - LOW HIGH HIGH - - - - - - - - - - - - ACTIVE EDGE - - rising rising - rising - - falling - - - - - - - - - - - - - - - - - - - - - - - DESCRIPTION IDD 1.5 mA - - - - - - - - - - 1.5 mA - 1.5 mA 3 mA 1.5 mA 1.5 mA 1.5 mA - - - - - - - - - - - - - -
PCF50732
audio digital interface PCM data output to DSP audio digital interface PCM data input from DSP audio digital interface PCM frame synchronization signal from DSP audio digital interface PCM clock signal from DSP asynchronous reset input low-swing master clock input; fclk = 13 MHz; integrated capacitive coupling digital power supply digital ground control bus clock input from DSP control bus data enable from DSP control bus data input from DSP control bus data output to DSP status control signal for activation of AUXDAC1, AUXDAC2 and MCLK input general purpose output pin baseband interface data clock baseband transmit interface data enable signal baseband interface data I/O from/to DSP baseband receive interface data enable signal baseband transmit path activation signal baseband receive path activation signal (I) baseband differential positive input/output to IF circuit (I) baseband differential negative input/output to IF circuit (Q) baseband differential positive input/output to IF circuit (Q) baseband differential negative input/output to IF circuit baseband power supply (analog) baseband ground (analog) auxiliary ADC input 1 for battery voltage measurement auxiliary ADC input 2 auxiliary ADC input 3 auxiliary ADC input 4 auxiliary DAC output for AGC; max. load 50 pF // 2 k auxiliary DAC output for AFC; max. load 50 pF // 10 k
1999 May 03
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Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
PCF50732
PIN SYMBOL AUXDAC3 VDDA(ref) VSSA(ref) Vref VDDA(vb) AUXMICP AUXMICN MICP MICN VSSA(vb) BUZ AUXSP EARN EARP VDDA(vbo) VSSA(vbo) Note 1. O/TS = 3-state output. NR. TYPE(1) 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 O P G I/O P I I I I G O O O O P G ACTIVE LEVEL - - - - - - - - - - - - - - - - ACTIVE EDGE - - - - - - - - - - - - - - - - DESCRIPTION IDD - - - - - - - - - - - - - - - - auxiliary DAC output for power ramping; maximum load 50 pF, 600 A reference voltage power supply (analog) reference voltage ground (analog) band gap reference voltage noise decoupling voice band voltage power supply auxiliary microphone differential positive input auxiliary microphone differential negative input microphone differential positive input microphone differential negative input voice band ground buzzer output auxiliary speaker output earphone differential negative output earphone differential positive output voice band output buffer voltage power supply (analog) voice band output buffer ground (analog)
1999 May 03
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Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
PCF50732
39 AUXMICN
38 AUXMICP
37 VDDA(vb)
42 VSSA(vb)
handbook, full pagewidth
47 VDDA(vbo)
48 VSSA(vbo)
44 AUXSP
45 EARN
46 EARP
41 MICN
40 MICP
43 BUZ
ADO
1
36 Vref 35 VSSA(ref) 34 VDDA(ref) 33 AUXDAC3 32 AUXDAC2
ADI 2 AFS 3 ACLK 4 RESET 5 MCLK 6 VDDD 7 VSSD 8 CCLK 9 CEN 10 CDI 11 CDO 12
PCF50732
31 AUXDAC1 30 AUXADC4 29 AUXADC3 28 AUXADC2 27 AUXADC1 26 VSSA(bb) 25 VDDA(bb)
AUXST 13
AMPCTRL 14
BIOCLK 15
BIEN 16
BDIO 17
BOEN 18
TXON 19
RXON 20
QN 24
IP 21
IN 22
QP 23
MGR989
Fig.2 Pin configuration.
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Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
8 FUNCTIONAL DESCRIPTION 8.2
PCF50732
Baseband and voice band reference voltages
This chapter gives a brief overview of the device. The detailed functional description can be found in the following chapters: Chapter 9 "Baseband CODEC" Chapter 10 "Voice band CODEC" Chapter 11 "Auxiliary functions" Chapter 12 "Control Serial Interface (CSI)" Chapter 13 "Voice band Signal Processor (VSP)". 8.1 General
The reference voltage Vref is generated on-chip by a band gap voltage reference circuit and is available at pin Vref. As Vref is used as reference for most of the internal analog circuitry, noise must be kept as low as possible by connecting an external decoupling capacitor at this pin. The voltage at Vref is buffered to generate the baseband and voice band reference voltage Vref as well as internal references for the different functions, such as the auxiliary and the transmit DACs. 9 BASEBAND CODEC
As low power consumption in mobile telephones is a very important issue, all the circuit parts in the PCF50732 can be powered-on/off either by means of the external signals AUXST, TXON or RXON, or by programming the respective register bits in the Control Serial Interface (CSI). The most important signal for the digital and analog circuit functions in the PCF50732 is the DAC enable signal AUXST, which allows to activate AUXDAC1 (AGC) and AUXDAC2 (AFC), as well as the low-swing master clock input MCLK. AUXST must be active (HIGH) and VDDA must be stable (see also Section 18.1) to allow the master clock to access different circuit parts after a reset (RESET active). AUXDAC1 and AUXDAC2 are only activated if their related power-on bit is set. AUXDAC1 is default off, AUXDAC2 is default on. RESET must be active during at least 3 MCLK cycles, with AUXST active, to ensure a correct initialisation of all the digital circuitry of the PCF50732. Since RESET is asynchronous even small spikes of a few nanoseconds can cause partial resets. For power supply noise interference reduction, a pair of power supply and ground pins are provided for the: * Baseband analog: VDDA(bb)/VSSA(bb) * Voice band analog: VDDA(vb)/VSSA(vb) * Voice band output drivers: VDDA(vbo)/VSSA(vbo) * DC reference voltages and currents: VDDA(ref)/VSSA(ref) * Digital circuitry: VDDD/VSSD. All VSS pins are connected internally. VDDD is the digital supply. VDDA(bb), VDDA(vb), VDDA(vbo), and VDDA(ref) are analog supplies, and are referred to as VDDA throughout this document. These analog supplies must be connected externally.
The baseband CODEC is a complete interface circuit between the RF part in a mobile communication handset and the digital signal processor. It consists of three parts: * The transmit path, which converts a bitstream to analog quadrature signals for the RF devices * The receive path, which transforms the quadrature signals of the IF chip (I/Q) to digital signals * The digital baseband serial interface, which exchanges baseband data between the PCF50732 and the DSP. The interface also includes signals to power-up and power-down the baseband transmit (TX) and receive (RX) paths. 9.1 Baseband transmit path
The baseband transmit path consists of three parts: * GMSK modulator: generation of a Gaussian Minimum Shift Keying (GMSK) signal * 10-bit DACs: digital-to-analog converters for the I and Q components of the GMSK signal * Low-pass filters: analog reconstruction low-pass filters for the output of the DACs. The requirements of the transmit path of a GSM terminal are given by "GSM recommendation 05.05": * Phase RMS error <5 * Phase peak error <20 * Amplitude error < 1 dB. Nevertheless the performance of the PCF50732 is far better than these figures indicate; see Section 18.1.
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Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
9.1.1 GMSK MODULATOR
PCF50732
The input signal of the GMSK modulator is a bitstream coming from the baseband serial interface, with a sampling frequency of 270.833 kHz. Typically 148 bits are modulated during a normal burst, and 88 bits during an access burst. Using this bitstream, the GMSK modulator generates digital I and Q components as described in "GSM recommendation 05.04". This is done in three steps: 1. First the incoming bitstream is differentially encoded by an EXOR operation on the actual bit and the previous bit 2. The instantaneous phase () is calculated using a gaussian filter with an impulse response of 4 taps 3. A look-up table provides the cosine (I component) and the sine values (Q component) of the phase (). The look-up table also interpolates the signal to a 16 times higher frequency (4.333 MHz). 9.1.2 10-BIT DACS
The baseband receive section can be switched between two modes of operation: * ZIF (zero IF) mode for radio sections, which convert the receive signal down to baseband. In this mode the ADC is sampled at 6.5 MHz, the decimation filter samples down by a factor of 24 with a pass band as specified in Fig.3. The serial interface output BDIO delivers 2 x 12-bit values for I and Q components at 270.833 kHz. * NZIF (near zero IF) mode for radio sections, which converts the receive signal down to a centre frequency of 100 kHz. In this mode the ADC is sampled at 13 MHz, the decimation filter samples down by a factor of 24 with a pass band as specified in Fig.3. The serial interface output BDIO delivers 2 x 12-bit values for I and Q components at 541.667 kHz. 9.2.1 RECEIVE ADC
The receive ADCs are analog-to-digital converters that convert differential input signals into1-bit data streams with a sampling frequency of 6.5 or 13 MHz. 9.2.2 DIGITAL DECIMATION FILTER
The two 10-bit DACs are working at a sampling rate of 4.3333 MHz. They convert the digital I and Q components of the GMSK modulator to differential analog I and Q signals. 9.1.3 LOW-PASS FILTER
Digital filtering is required for: * Suppression of out-of-band noise produced by the ADC * Decimation of the sampling rate (6.5 or 13 MHz) by 24 * System level filtering. The digital filtering is performed by a digital FIR filter with a group delay for this running average filter of approximately 23 or 11.5 s respectively. The filter uses twos complement arithmetic.
The analog output signals of the DACs are filtered by analog reconstruction low-pass filters. These filters remove high frequency components of the DAC output signals and attenuate components around the 4.3333 MHz sampling frequency. The low-pass filters have a cut-off frequency of approximately 300 kHz, with very linear phase behaviour in the pass band. 9.2 Baseband receive path
The baseband receive path consists of two parts: * Receive ADC: analog-to-digital converters * Decimation filter: digital decimation filters for I and Q.
1999 May 03
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Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
PCF50732
handbook, full pagewidth
20
MBL025
gain (dB) 0
-20 ZIF -40 NZIF
-60
-80
-100 0 100 200 300 400 500 f (kHz) 600
3
Fig.3 Transfer functions for the baseband receive filter.
9.3 9.3.1
Baseband Serial Interface (BSI) OVERVIEW
The digital part of the baseband consists of a receive section and a transmit section. The receive section is a FIR filter that reduces the 6.5 MHz (13 MHz for NZIF mode) bitstream from the sigma-delta converters into 2 x 12-bit values at 270.833 kHz (541.667 kHz for NZIF mode). The transmit section converts the 270.833 kHz data stream from the DSP into a GMSK signal sampled at 4.333 MHz. The 10-bit I and Q signals are then fed into two 10-bit DACs. The power ramping signal is also generated by the transmit section with the 10-bit AUXDAC3 block. 9.3.2 TRANSMIT PATH BLOCK DESCRIPTION
BIEN0 must be at least 10 quarterbits long to allow settling of the analog filters. Bits are clocked out of the DSP by the falling edge and clocked into the PCF50732 by the rising edge of BIOCLK. After the BIEN1 period has elapsed, BIEN is set HIGH again and transmission from the DSP ends. Logic 1s are modulated whenever BIEN is HIGH and the baseband transmit (BBTX) block is active. Values for BIEN0 and BIEN1 can be set in the Burst control register. Figure 5 shows the timing for the BSI data transmission. In power-down the de-asserted value of BIOCLK is high-Z and BIEN is HIGH. Typical connection to the system DSP is defined in Table 1. Table 1 Connection of BSI transmit signals to PCF5087X PCF50732 PIN TXON BDIO BIEN BIOCLK I/O I I/O O O PCF5087X PIN RFSIG[y] SIOXD SOXEN_N SIOXCLK I/O O I/O I I
9.3.2.1
Transmit serial interface
The power-up of the BSI transmit path is controlled via the TXON pin. When TXON is pulled HIGH, the transmit path recovers from power-down. The MCLK/48 = 270.833 kHz output signal BIOCLK is activated. When the BIEN0 period has elapsed the output signal BIEN goes LOW and the bits to be transmitted are clocked out of the DSP. 1999 May 03 11
Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
9.3.2.2 Power ramping controller
PCF50732
The PCF50732 fully supports all multislot modes which do not require full duplex operation or more than two consecutive transmit bursts. In this specification double burst mode is used for all supported multislot modes while single burst mode supports the normal GSM modes. The power ramping controller drives the power amplifier output envelope. In each transmit (TX) burst one ramp-up and one ramp-down will be carried out. In multislot mode one intermediate ramp will be carried out in addition to ramp-up and ramp-down. Each ramp consists of 16 discrete step values that are sent to the DAC3. Each step's duration is 2 quarterbits which translates into 8-bit long ramps. The DAC3 output is in 3-state whenever it is powered down. The ramping step values are stored in a 64 x 10-bit RAM as shown in Table 2. In order to initialize AUXDAC3 it is necessary to write into the RAM all 32 (or 48 in multislot mode) DAC3 output values. Filling the RAM is normally done by writing a logic 0 to the address sub-register of the Burst control register, after which 32 or 48 values, depending on multislot mode, can be written into the data sub-register of the Burst control register. Writing to the DAC3 RAM is only possible when the DAC3 is powered off. Total number of CSI-accesses is therefore 33 for a normal burst and 49 for a double burst. An autoincrement feature will store these data into the correct RAM positions. The value after power-up of DAC3 will always be equal to the value of RAM location 47. AUXDAC3 timing is controlled by the Burst control register. This contains the following sub-registers: * The RU register containing the delay in number of quarterbit cycles from the assertion of TXON to the start of the power-up ramping; default value is 0 * The RM register containing the delay in number of quarterbit cycles from the assertion of TXON to the start of the intermediate power ramp; default value is 0. RM is only used in case of multislot mode * The RD register containing the delay in number of quarterbit cycles from the assertion of TXON to the start of the power-down ramping; default value is 0 * DAC3 burst RAM address register * DAC3 burst RAM data register * Single/double burst mode register: normal mode or multislot mode selection flag. 1999 May 03 12
After TXON goes HIGH and a time equal to RU quarterbit periods has elapsed, power ramp-up is done. After a time period equal to RD quarterbits has elapsed power ramp-down is initiated. The AUXDAC3 output is also shown in Fig.4. Values for RU (ramp-up) and RD (ramp-down) can be set in the Burst control register of the control serial interface. RD must be greater than RU + 32. RU and RD range from 0 to 4000 QB (quarterbit). The register offers the possibility to enter codes up to 4095. The GMSK modulator is active for a period of 2 clock cycles after the ramp-down or for the length of the TXON burst, whichever is longer. Multislot (high speed switched data mode) can be selected by setting the appropriate bit in the Burst control register. In multislot mode an intermediate ramping step is done. This intermediate step is started after a time period equal to RM quarterbits has elapsed. A value for RM (intermediate ramp) is also set using the Burst control register. The following conditions must be true: RU + 32 < RM and RM + 32 < RD. Table 2 AUXDAC3 RAM contents DATA ramp-up data intermediate ramp data ramp-down data not used
RAM ADDRESS 0 to 15 16 to 31 32 to 47 48 to 64 Table 3
Power ramping timing characteristics VALUE 12t1 RU register RM register RD register 32t0 COMMENTS(1) one quarterbit (QB) 0 to 4000 QB RU + 32 to 4000 QB RM + 32 to 4000 QB 8 bits; 32 QB
SYMBOL t0 tru tim trd trup, trim, trdo Note
1. QB: Quarterbit, usually referred to the time needed for one quarter of a GSM baseband bit, i.e. a frequency of 1 x 13 MHz. 12
Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
PCF50732
handbook, full pagewidth
TXON
APE_DAC3(1) t im t ru AUXDAC3
t rd ADDRESS AUXDAC3 RAM 0 47 47 t rup 15 15 t rim 15 31 31 t rdo 31 47 47
MGR995
RU
RM
RD
(1) APE_DAC3: Analog Power Enable signal for the AUXDAC3.
Fig.4 Power ramping timing characteristics (multislot mode).
9.3.3
RECEIVER PATH BLOCK DESCRIPTION
9.3.3.1
Receive serial interface
The baseband serial interface sends the digital signal of the receive path to a digital signal processor. It also takes the digital bitstream from the digital signal processor and transmits it via the baseband CODEC. The baseband reception and transmission are active in bursts. A normal burst has a length of 548 s. The frame rate of bursts is 4.615 ms. Using a normal traffic channel, one burst for each frame is transmitted and two bursts are received. To save as much power as possible, the transmit path and the receive path of the PCF50732 are in power-up mode only during the transmission or reception bursts respectively. The power-up of the receive section is controlled via the RXON pin or RXON bit. When RXON is driven HIGH, the receive section recovers from power-down and the output clock BIOCLK is activated. After a settling delay of 52 s (ZIF mode, analog circuitry + decimation filter settling time), BOEN goes LOW to transfer the first 12-bit I and Q words. The settling time is only 26 s in NZIF mode.
Bits are clocked out of the PCF50732 by the falling edge, and clocked into the DSP by the rising edge of BIOCLK. In normal bursts 148 I/Q pairs are read from the PCF50732. When RXON goes LOW, the last pair of I and Q values will be sampled and transferred to the baseband processor (both I and Q components). BIOCLK stops after additional 16 BIOCLK cycles. The receive path is powered down again. In power-down the BIOCLK output is put in 3-state and the BOEN output is HIGH. The output format is 2 x 12-bit I/Q (twos complement). Transmission occurs MSB first, I followed by Q. The serial clock signal BIOCLK will run at 6.5 MHz, or 13 MHz in the NZIF mode. Figure 6 shows the timing of the BSI data reception. An automatic offset compensation mechanism is provided in order to achieve the required performance. This mechanism will short the receive (RX) inputs internally and measure the resulting offset value. This offset value will be subtracted from all subsequent I/Q output words. The offset inherent to the device can thereby be reduced to a few millivolts. Default value for both I- and Q-offset is zero.
1999 May 03
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Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
Offset compensation measurement can be done on three channels separately: baseband receive I channel, baseband receive Q channel and AUXADC channel. All AUXADC channels use the same offset compensation value. Starting an offset measurement is done by writing a logic 1 into the offset trigger register for each channel that needs calibration. If the value `7' (decimal) is written into the offset trigger register offsets will be measured for I, Q and AUXADC channels. Offsets can also be read or written directly. Each offset measurement is implemented internally as an AUXADC measurement and takes approximately 100 s. Offsets from -256 up to 255 can be compensated. 9.3.4 Table 4
PCF50732
Connection of BSI receive signals to the PCF5087X PCF50732 PIN RXON BDIO BOEN BIOCLK I/O I I/O O O PCF5087X PIN RFSIG[z] SIOXD SIXEN_N SIOXCLK I/O O I/O I I
BASEBAND SERIAL INTERFACE (BSI) TIMING CHARACTERISTICS
intermediate ramp ramp-up 32 QB t 44 32 QB ramp-down 32 QB trail 2 BIOCLK clocks
handbook, full pagewidth
t 43 t 42
t 40 TXI/Q(1) logic 1s data data data
data
logic 1s
AUXDAC3 t7 BIOCLK high-Z high-Z
BDIO
high-Z
d.c.(2) t 39
d.c.
d.c.
B(0)
B(1) t9 t10
B(n)
high-Z
BIEN t5 TXON t6
MGR990
(1) TXI/Q = transmit I or Q. (2) d.c. = don't care; will be overwritten with logic 1.
Fig.5 Timing of the baseband serial interface transmit path; for the timing values see Table 5
1999 May 03
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Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
PCF50732
handbook, full pagewidth
t12
16t1 high-Z
high-Z BIOCLK
BDIO t13 BOEN
I11 t14
I0
Q11
Q0
t15 RXON
MGR991
t11
548 s
Fig.6 Timing of the baseband serial interface receive path; for the timing values see Table 5.
Table 5
BSI timing characteristics PARAMETER - 30 30 3t1 10 t5 - 20 20 - - 0 32 + t42 32 + t42 32 + t43 MIN. TYP. - - - - MAX. UNIT
SYMBOL Master clock t1 t2 t3 t4 t5 t6 t7 t9 t10 t39 t40 t42 t43 t44 MCLK cycle time MCLK LOW time MCLK HIGH time RESET LOW time
76.9
1 1 2t1 2t1
ns ns ns ns
- - - 48t1 - - - - - - - -
Baseband Serial Interface (BSI) transmit path (see Fig.5) BIEN0 value BIEN1 value BIOCLK cycle time data set-up time data hold time BIOCLK active after TXON rising edge analog TX and GMSK power-up time ramp-up value intermediate ramp value ramp-down value normal mode double burst mode 4020 4020 QB QB 511 4000 - - - t1 17.4 3940 3980 QB QB ns ns ns ns QB QB QB
1999 May 03
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Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
PCF50732
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
Baseband Serial Interface (BSI) receive path (see Fig.6) t11 analog power-up and filter settling time ZIF mode NZIF mode t12 BIOCLK cycle time ZIF mode NZIF mode t13 t14 t15 BOEN LOW after falling clock edge BIOCLK falling edge to data valid BOEN HIGH after falling clock edge - - - - - 2t1 t1 - - - - - 15 15 15 ns ns ns ns ns - - 52 26 - - s s
10 VOICE BAND CODEC The voice band CODEC is a complete analog front-end circuit. It consists of three parts: * The receive path, which converts a digital linear PCM signal to an analog signal for an earpiece, an external loudspeaker or a buzzer * The transmit path, which receives an analog signal from a microphone or an auxiliary input and converts it into a digital linear PCM signal * The digital Audio Serial Interface (ASI), which connects the digital linear PCM signals of the receive and transmit paths to a digital signal processor. Various functions and characteristics of the voice band CODEC can be selected by programming the corresponding control registers in the Control register block (see also Tables 11, 22, 23, 24 and 25). 10.1 Voice band receive path
Linearity of receiver equipment (to earpiece) at EARPGA = 0 dB and a volume control (VOLPGA and EARAMP or AUXAMP) of -12 dB, signal-to-total harmonic distortion ratio according to "GSM recommendation II.11.10 V.4.16.1". 10.1.1 RXVOL
RXVOL controls the volume of the voice band receive path. In conjunction with EARAMP, AUXAMP and BUZAMP it allows a gain variation from +6 to -30 dB in 64 steps; see Table 25. RXVOL also provides a mute selection of the three outputs EARP/EARN, AUXSP and BUZ respectively. At RESET the volume is automatically set to -12 dB. 10.1.2 RXPGA
RXPGA controls the gain of the voice band receive path within a range of -24 to +12 dB in 64 steps for calibration purposes. 10.1.3 RXFILTER
The voice band receive path consists of the following parts: * The receive part of the voice band signal processor * NOISE SHAPER: 3rd order digital modulator, generates a bit stream at 1 MHz to drive the EARDAC * EARDAC: digital-to-analog converter including low-pass filter for high frequency noise content of noise shaper * EARAMP: amplifier for an earpiece * AUXAMP: amplifier for an auxiliary loudspeaker * BUZAMP: amplifier for a buzzer output.
RXFILTER is a digital band-pass filter with a pass band from 300 to 3400 Hz. It is realized by a programmable structure (voice band signal processor). 10.1.4 EARDAC
EARDAC is a DAC operating at a sampling frequency of 1 MHz. It converts the bitstream input to a sampled differential analog signal and low-pass filters the output signal at the same time.
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Philips Semiconductors
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Baseband and audio interface for GSM
10.1.5 EARAMP
PCF50732
EARAMP is an amplifier, capable of driving a standard earpiece with a minimum impedance of 8 in single-ended mode or 16 in differential mode. 10.1.6 AUXAMP
Values are specified for a standard electret microphone with a sensitivity of -64 3 dB for high gain or for an external microphone with an amplifier sensitivity of -26 3 dB (0 dB 1 V/0.1 Pa = 1 V/bar; at 1 kHz). 10.2.2 MICADC
AUXAMP is an amplifier for connection to an external loudspeaker amplifier of minimum 8 (hands-free car kit). An `auxiliary speaker external amplifier control' output pin (AMPCTRL) can be used to switch on/off an external amplifier (hands-free car kit). The status of AMPCTRL is programmable via the Control Serial Interface; its default value is on. 10.1.7 BUZAMP
MICADC is a A/D converter which generates a 1 MHz bitstream. 10.2.3 DECIMATOR AND TXFILTER
The DECIMATOR is a digital filter, which performs a signal processing to a lower sampling rate at the output compared to the input. The bitstream with a sampling frequency of 1 MHz is low-pass filtered and down-sampled to 40 kHz by a FIR filter. A digital high-pass filter and a digital low-pass filter (both IIR filters) process the 14-bit input samples to achieve a band-pass with a pass band from 300 to 3400 Hz. These filters run on the on-chip voice band signal processor (see Fig.7). It's program is down-loaded into the instruction memory (IRAM) via the CSI (see Table 26). The output of the TXFILTER is down-sampled to a sampling frequency of 8 kHz with a word length of 16 bits. 10.2.4 TXPGA
BUZAMP is an amplifier for connection to an external buzzer of minimum 8 . It has the same output characteristics as the AUXAMP and can hence be used as a second auxiliary output amplifier. It is switched on/off by a dedicated control bit in the Control register block. 10.2 Voice band transmit path
The voice band transmit path consists of the following parts: * MICMUX: microphone input multiplexer * MICADC: analog-to-digital converter * DECIMATOR: decimates the incoming bit stream from 1 MHz to 40 kHz * TXFILTER: band-pass filter for the digital transmit signal and down-sampling * TXPGA/LIM: fine-programmable gain for calibration, limiter * SidePGA: voice band sidetone programmable gain amplifier. Linearity of transmitter equipment, signal-to-total harmonic distortion ratio according to "GSM recommendation II.11.10 V.4.16.1". 10.2.1 MICMUX
TXPGA adapts the analog signals coming from MICMUX within a range of -30 to +6 dB. It is designed for calibration purposes. 10.2.5 SIDEPGA
SidePGA loops part of the voice band transmit signal back into the receive path. There are 64 gain steps from mute to +6 dB. 10.3 Voice band digital circuitry
MICMUX is used to select between a differential signal at pins MICP/MICN and a differential signal at pins AUXMICP/AUXMICN.
The voice band digital circuitry is responsible for converting a 16-bit PCM signal at 8 kHz sample rate to and from a 1-bit 1 MHz signal. It also contains a band-pass filter for 300 to 3400 Hz and a sidetone engine. Various volume settings are calculated inside this block. Figure 7 shows the block diagram of the voice band signal processor.
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Philips Semiconductors
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Baseband and audio interface for GSM
PCF50732
handbook, full pagewidth
VOICE BAND SIGNAL PROCESSOR ADI ACLK ASI AFS ADO 16-bit, 8 kHz RXVOL RXPGA/LIM NOISE SHAPER
MGR992
TXPGA/LIM
DECIMATOR
TX_BS (transmit bitstream)
SidePGA
RX/TX FILTER
1-bit, 1 MHz
RX_BS (receive bitstream)
RRAM
IRAM
Fig.7 Block diagram of the voice band signal processor.
10.3.1
VOLUME CONTROL BLOCK
The volume control block contains the RXPGA, SidePGA, TXPGA and both limiter blocks. The possible settings can be found in the description of the CSI block. All digital volume control blocks, i.e. RXPGA, SidePGA, and TXPGA, will allow settings from +6 to -30 dB and mute in 64 steps. However, not all combinations of settings for these blocks will be meaningful. The limiter will always clip signals with overflow to the maximum or minimum allowable value. 10.3.2 AUDIO SERIAL INTERFACE (ASI) BLOCK
Pin ADO is put in 3-state after the LSB of the transmit word, independent of the length of the AFS pulse. If the channel position 0 (see Section 10.3.2.1) is selected, then the MSB must be output directly after AFS becomes a logic 1, even if no rising edge on ACLK has been given yet. The following modes of operation are programmable: channel position and ACLK clock mode.
10.3.2.1
Channel position mode
The ASI is the voice band serial interface which provides the connection for the exchange of PCM data in both receive and transmit directions, between the baseband digital signal processor and the PCF50732. The data is coded in 16-bit linear PCM twos complement words. A frame start is defined by the first falling edge of ACLK after a rising AFS. This first falling edge is used to clock in the first data bit on both the baseband and the DSP device. Data on pin ADI is clocked in (MSB first) on the falling edge of the ACLK clock. Data is clocked out (MSB first) on pin ADO on the rising edge of the ACLK clock.
Depending on a programmable register value n (n = 0 to 15) one of 16 channels can be selected (see Table 22). The ASI can add a delay of 16 x n-bit clocks between the assertion of AFS and the start of the MSB of the PCM values. This delay is independently programmable for transmit and receive mode.
10.3.2.2
ACLK clock mode
Single or double clock mode can be selected. Double clock mode implies two clock pulses per data bit and is used for communication with IOM2 compatible devices. In double clock mode data must be output on the first rising edge and be read on the last falling edge.
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Philips Semiconductors
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Baseband and audio interface for GSM
Table 6 Pin connection of the audio serial interface to the PCF5087X PCF50732 PIN ADI ADO ACLK AFS I/O I O I I PIN DD DU DCL FSC PCF5087X
PCF50732
I/O O I O O
handbook, full pagewidth
AFS
ADI t rpdc ADO t tpdc
word
word
MGR993
trpdc: receive path data channel delay. ttpdc: transmit path data channel delay.
Fig.8 Frame structure of the Audio Serial Interface (ASI).
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Baseband and audio interface for GSM
10.3.2.3 Audio Serial Interface (ASI) timing characteristics
t 41
PCF50732
handbook, full pagewidth
AFS t16 t17
t 42 ACLK
t 21 MSB ADO single clock mode ADI last slot last bit t 19 last slot last bit t 21 MSB ADO double clock mode ADI last slot last bit last slot last bit first slot first bit t 19 MSB first slot first bit slot 1 bit 2 t 20 slot 1 bit 2 first slot first bit t 20 MSB first slot first bit first slot second bit first slot second bit t 18
t 40 LSB last slot last bit high-Z
LSB last slot last bit
LSB last slot last bit high-Z
LSB last slot last bit
MGR994
Fig.9 Timing of the Audio Serial Interface (ASI).
Table 7
ASI timing characteristics PARAMETER frame sync (AFS) set-up time to falling edge of ACLK frame sync (AFS) hold time from falling edge of ACLK ACLK rising edge to data (ADO) valid data (ADI) set-up time to falling edge of ACLK data (ADI) hold time from falling edge of ACLK first data valid (ADO) after AFS rising edge ACLK period single clock mode double clock mode 0.5 0.5 - 40 - - 125 - 7.8 3.9 - - s s s ns MIN. 70 40 -30 50 80 0 - - - - - - TYP. - - +30 - - 60 MAX. UNIT ns ns ns ns ns ns
SYMBOL t16 t17 t18 t19 t20 t21 t40
t41 t42
AFS period ACLK LOW before AFS rising edge
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Philips Semiconductors
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11 AUXILIARY FUNCTIONS The auxiliary functions part consists of three digital-to-analog converters (DACs) and a 4 input analog-to-digital converter (ADC) with a 12-bit range. The DACs are for: * Automatic Gain Control (AGC): AUXDAC1 * Automatic Frequency Control (AFC): AUXDAC2 * Power ramping: AUXDAC3. 11.1 Automatic Gain Control (AGC): AUXDAC1 11.3 Power ramping: AUXDAC3
PCF50732
AUXDAC3 is a 10-bit binary coded digital-to-analog converter designed for power ramping purposes. AUXDAC3 is default off. The power ramping behaviour is described in Section 9.3.2.2. 11.4 Auxiliary analog-to-digital converter (AUXADC)
The AUXADC is specified for voltage and temperature measurements. It contains 4 input channels required for T and V measurements, as well as battery type recognition: * T: battery temperature, ambient temperature (measured across sensor) * V: peak battery voltage, battery voltage during transmit burst. Five 12-bit registers are available in which results of auxiliary analog-to-digital conversions can be stored. Two registers are dedicated to the input AUXADC1 and one to each of AUXADC2, AUXADC3 and AUXADC4. The AUXADC1 input can be used for battery voltage measurement. In the AUXADC1A register the voltage during a transmit time slot can be stored. The AUXADC1B register can store the voltage during other time slots. If a read request to one of these registers is executed by loading its address into the Read request register, the actual contents of the addressed register are given to the control interface and a new measurement is performed in the next appropriate time slot. A multiplexer connects each of the AUXADC inputs to a channel of the receive ADC depending on read access to the corresponding register. Thus an auxiliary analog-to-digital conversion is only possible, if the baseband receive section is not in use (RXON is LOW). At each read request to one of the AUXADC registers, a flag is set in the AUXADC flag register indicating that an analog-to-digital conversion is to be performed. When one of the registers AUXADC1B, AUXADC2, AUXADC3, or AUXADC4 is being read, the baseband interface verifies that RXON is LOW, indicating that no receive burst is currently active. The baseband receive path is then powered up. After the ADC settling time has elapsed (see POSTAUXADC in Chapter 18), valid data is available and stored in the corresponding register.
The AUXDAC1 is an 8-bit binary coded, guaranteed monotonic digital-to-analog converter. The status of AUXDAC1 is controlled by the signal AUXST and a power-up bit in the Power control register. The signal that switches the external VCXO can also be used to control the AUXST pin of the PCF50732. The AUXDAC1 output is floating in Power-down mode (AUXST = LOW). The input MCLK is then deactivated. When AUXST goes HIGH, AUXDAC1 is powered-up and the converted value of the corresponding register in the control register block is available at the AUXDAC1 output pin. If a write access to the AUXDAC1 register occurs, the DAC is activated with the new content of the DAC register (see Table 14 and 15). The AUXDAC1 must be powered-up by setting the correct bit in the Power control register. At reset AUXDAC1 is powered-down. 11.2 Automatic Frequency Control (AFC): AUXDAC2
The AUXDAC2 is a 12-bit binary coded, guaranteed monotonic digital-to-analog converter. This DAC is used to control the frequency of an external master clock VCXO. The status of AUXDAC2 is controlled by the signal AUXST and a power-up bit in the Power control register. The signal that switches the external VCXO can also be used to control the AUXST pin of the PCF50732. The AUXDAC2 output is floating in Power-down mode (AUXST = LOW). When AUXST goes HIGH, AUXDAC2 is powered-up and the converted value of the corresponding register in the control register block is available at the AUXDAC2 output pin. The default value for AUXDAC2 is 1.1 V which corresponds to a 800H code in the AUXDAC2 register. At reset AUXDAC2 is powered on.
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Baseband and audio interface for GSM
After conversion the corresponding bit in the AUXADC flag register is reset (see Table 18). If RXON is activated during an auxiliary analog-to-digital conversion cycle, the auxiliary conversion is interrupted and restarted when RXON returns LOW, indicating no receive burst activity. When register AUXADC1A is read, a battery voltage measurement during a transmission burst is executed.
PCF50732
The PCF50732 waits for a rising edge of TXON, and powers up the receive path. After the settling time of the ADC added to the programmed AUXADC conversion delay (in 48 MCLK cycles) has elapsed, valid data is available and stored in the AUXADC1A register.
handbook, full pagewidth
1440
output code (LSB) gain tolerance
offset at 0 V
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8 Vin (V)
2.0
MGR996
Fig.10 Typical transfer characteristics of AUXADC (output code as function of differential input voltage).
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Philips Semiconductors
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Baseband and audio interface for GSM
12 CONTROL SERIAL INTERFACE (CSI) The Control Serial Interface block is used to set and read the status bits inside the PCF50732. It is also used to read data from the auxiliary ADCs and to write data into the auxiliary DACs. Finally, the block is used to write the power ramping curve into a 64 x 10-bit static RAM. It should be noted that only 48 of the 64 addresses can be accessed; see Table 2. 12.1 The serial interface
PCF50732
If the device address is equal to the chip address, the programmed information on CDI (DB11 to DB00) is loaded into the addressed register (RA3 to RA0) when CEN returns inactive HIGH. The dummy bit in front is needed for compatibility with older baseband devices. Reading a register is accomplished by writing the address of the required register into the read request register. The next time CEN goes LOW, the requested data will be shifted out, together with the register and device address. Table 8 Pin connection of the CSI to the PCF5087X PCF50732 PIN CDI CDO CCLK CEN Table 9 BIT I/O I O I I PCF5087X PIN RFDO RFDI RFCLK RFE_N2 I/O O I O O
A 4-line bidirectional serial interface is used to control the circuit. It allows access to each register of the control register block (read and/or write). The 4 lines are: * Data in (CDI) * Data out (CDO) * Clock (CCLK) * Enable (CEN). Table 8 lists the normal connections to the PCF5087X. The data sent to or from the device is loaded in bursts framed by CEN. Clock edges and data bits are ignored until CEN goes active (LOW). Each data word consists of 21 bits that comprises a 4-bit device address, a 4-bit register address, a 12-bit data word and a dummy bit; see Table 9. The 21 bits are transmitted with MSB first. Figure 5 shows the valid timing for data transmission on the control interface. Data is read in from the CDI pin on the rising edge of the CCLK clock and output on CDO on the falling edge of the CCLK clock. Data is written into the registers on the rising edge of CEN.
Bit mapping of the 21-bit words CONTENT DESCRIPTION
00 to 03 ADD0 to ADD3 device address; for the PCF50732 this is `1001' (= 9 decimal) 04 to 07 RA0 to RA3 08 to 19 DB00 to DB11 20 dummy register address data value don't care
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Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
12.2 Control Serial Interface (CSI) timing characteristics
PCF50732
handbook, full pagewidth
CCLK t 22 CEN t 25 CDI dummy t 23 CDO dummy MSB(#19) t 26 ADD0(#0) t 23 ADD0(#0) high-Z t 38 t 24 t 27
MSB(#19)
t 37
MGR997
Fig.11 Timing diagram of the Control Serial Interface (CSI).
Table 10 CSI timing characteristics For the timing diagram see Fig.11. SYMBOL t22 t23 t24 t25 t26 t27 t37 t38 CEN set-up time CDO data valid after falling clock edge CCLK cycle time data set-up time to rising edge of CCLK data hold time from rising edge of CCLK CEN hold time CDO 3-state after CEN HIGH CEN HIGH time PARAMETER - 100 20 30 30 - 50 MIN. 20 - 50 - - - - 30 - MAX. UNIT ns ns ns ns ns ns ns ns
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12.3 Control register block
PCF50732
This section describes the different registers that are implemented in the PCF50732. An overview is given in Table 11. Tables 12 to 29 describe all the registers of the PCF50732. Table 11 Control register block overview ADDRESS 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Notes 1. See description in Section 11.4. 2. Do not use this register. 12.3.1 READ REQUEST REGISTER ACCESS W R/W R/W R/W R/W R R R R R R/W R/W R/W R/W R/W R/W Read request register AUXDAC1 (AGC) value register AUXDAC2 (AFC) value register Burst control register AUXADC control register AUXADC channel 1 register A (AUXADC1A); note 1 AUXADC channel 1 register B (AUXADC1B); note 1 AUXADC channel 2 register (AUXADC2); note 1 AUXADC channel 3 register (AUXADC3); note 1 AUXADC channel 4 register (AUXADC4); note 1 Voice band control register Voice band volume register Power control register RAM interface register Baseband receive control register Test mode register; note 2 REGISTER NAME
Table 12 Read request register X = don't care during a read/or write access. VALUE ADDRESS 0000 REGISTER NAME 11 Read request register X 10 X 9 X 8 X 7 r3 6 r2 5 r1 4 r0 3 s3 2 s2 1 s1 0 s0
Table 13 Read request registers value description VALUE OF Read request register SYMBOL r3 to r0 s3 to s0 DESCRIPTION Address of the register to be read. Subaddress that might be needed. The subaddress bits are right aligned, meaning that the subaddress always starts with bit `s0' (LSB); e.g. in case of two subaddress bits, `s1' and `s0' are used.
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Baseband and audio interface for GSM
12.3.2 AUXDAC1 (AGC) VALUE AND AUXDAC2 (AFC) VALUE REGISTERS
PCF50732
Table 14 Registers overview X = don't care during a read/or write access. VALUE ADDR. 0001 0010 REGISTER NAME 11 AUXDAC1 (AGC) value register AUXDAC2 (AFC) value register X b11 10 X b10 9 X b9 8 X b8 7 b7 b7 6 b6 b6 5 b5 b5 4 b4 b4 3 b3 b3 2 b2 b2 1 b1 b1 0 b0 b0
Table 15 AUXDAC1 (AGC) value and AUXDAC2 (AFC) value registers value description VALUE OF SYMBOL DESCRIPTION input value to the 8-bit AUXDAC1 (fed directly into the DAC); the default value is 85H input value to the 8-bit AUXDAC2 (fed directly into the DAC); the default value is 800H
AUXDAC1 (AGC) value register b7 to b0 AUXDAC2 (AFC) value register b11 to b0
12.3.3
BURST CONTROL REGISTER
The Burst control register controls the timing of the transmit burst (TX-burst). The `lo'-registers contain the lower 8 bits, the `hi'-registers the upper 4 bits of a 12-bit delay value. Therefore, each register has a programmable range from 0 to 4095. Not all combinations of values might make sense e.g. ramp-down before ramp-up. Table 16 Burst control register (address 001 and subaddresses) X = don't care during a read/or write access. SUBADDRESS FUNCTION RU-lo RU-hi RM-lo RM-hi RD-lo RD-hi BIEN0-lo BIEN0-hi BIEN1-lo BIEN1-hi Single/double burst DAC3 burst RAM DAC3 burst RAM Notes 1. The programming is described in Section 9.3.2.2. 2. The subaddress positions bit 9 (s1) and bit 8 (s0) do not apply to the DAC3 burst RAM data register. mode(1) address(1) data(1) 11 (s3) 0 0 0 0 0 0 0 0 1 1 1 1 1 10 (s2) 0 0 0 0 1 1 1 1 0 0 0 0 1 9 (s1) 0 0 1 1 0 0 1 1 0 0 1 1 d9(2) 8 (s0) 0 1 0 1 0 1 0 1 0 1 0 1 d8(2) 7 b7 X b7 X b7 X b7 X b7 X X X d7 6 b6 X b6 X b6 X b6 X b6 X X X d6 5 b5 X b5 X b5 X b5 X b5 X X a5 d5 VALUE 4 b4 X b4 X b4 X b4 X b4 X X a4 d4 3 b3 b11 b3 b11 b3 b11 b3 b11 b3 b11 X a3 d3 2 b2 b10 b2 b10 b2 b10 b2 b10 b2 b10 X a2 d2 1 b1 b9 b1 b9 b1 b9 b1 b9 b1 b9 X a1 d1 0 b0 b8 b0 b8 b0 b8 b0 b8 b0 b8 b0 a0 d0
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Table 17 Burst control registers value description VALUE OF RU DESCRIPTION
PCF50732
Value RU, consisting of RU-lo (least significant byte) and RU-hi (most significant byte), is the delay measured in quarterbits (112MCLK) between the rising edge of TXON and the start of the ramp-up on AUXDAC3. After this delay, the first 16 values of the AUXDAC3 RAM are sent to AUXDAC3. Shifting out is done at 124MCLK. Value RM, consisting of RM-lo (least significant byte) and RM-hi (most significant byte), is the delay measured in quarterbits between the rising edge of TXON and the start of the intermediate ramp in a double burst ramp. The RM value is only used in multislot mode. RM must be greater than RU + 32. Value RD, consisting of RD-lo (least significant byte) and RD-hi (most significant byte), is the delay measured in quarterbits between the rising edge of TXON and the start of the ramp-down on AUXDAC3. RD must be greater than RU + 32, or in case of multislot mode, greater than RM + 32. Value BIEN0, consisting of BIEN0-lo (least significant byte) and BIEN0-hi (most significant byte), is the delay measured in quarterbits between the rising edge of TXON and the falling edge of BIEN. Value BIEN1, consisting of BIEN1-lo (least significant byte) and BIEN1-hi (most significant byte), is the delay measured in quarterbits between the rising edge of TXON and the rising edge of BIEN. BIEN1 must be greater than BIEN0. AUXADC CONTROL REGISTER
RM
RD
BIEN0 BIEN1
12.3.4
Table 18 AUXADC control register (address 0100 and subaddresses) X = don't care during a read/or write access. SUBADDRESS FUNCTION AUXADC conversion delay value register AUXADC flag register AUXADC offset value register I channel offset value register Q channel offset value register Offset trigger register 11 (s2) 0 0 1 1 1 1 10 (s1) 0 0 0 0 1 1 9 (s0) 0 1 0 1 0 1 X X 8 X X 7 X Qoff 6 b6 Ioff 5 b5 auxoff VALUE 4 b4 flag 4 3 b3 flag 3 2 b2 flag 2 1 b1 0 b0
flag 1B flag 1A
9-bit signed offset compensation value 9-bit signed offset compensation value 9-bit signed offset compensation value X X X X Q-off I-off Aux
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Baseband and audio interface for GSM
Table 19 AUXADC control registers value description VALUE OF AUXADC conversion delay value register AUXADC flag register DESCRIPTION
PCF50732
The 7-bit value (b6 to b0) denotes the delay measured in 48MCLK units between the rising edge of TXON and the conversion on AUXADC1A. The normal power-on settling time is added to this delay. Default value is 0. The AUXADC flag register returns the status of the AUXADC converters. If an auxiliary A/D conversion is pending, the flag of the corresponding AUXADC will be set. The flag register is read only.
AUXADC offset value register I channel offset value register
The offset value registers contain signed 9-bit offset compensation values. These values are subtracted automatically from all baseband receive (BBRX) and AUXADC measurements to compensate for offset errors. The compensation values can be Q channel offset value register read and written and have a default value of 0. It can also be measured by the device Offset trigger register itself. A write to the Offset trigger register will trigger an offset measurement for each of the channels (Q-off, I-off or AUXADC) selected. Offset measurements are special cases of AUXADC measurements and are done sequentially. Each calibration measurement takes approximately 100 s. The Offset trigger register is write only.
12.3.5
AUXADC REGISTERS
Table 20 AUXADC registers overview VALUE ADDR. 0101 0110 0111 1000 1001 REGISTER NAME 11 AUXADC channel 1 register A (AUXADC1A) AUXADC channel 1 register B (AUXADC1B) AUXADC channel 2 register (AUXADC2) AUXADC channel 3 register (AUXADC3) AUXADC channel 4 register (AUXADC4) b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 10 9 8 7 6 5 4 3 2 1 0
Table 21 AUXADC registers value description VALUE OF DESCRIPTION
AUXADC1A 12-bit result of the A/D conversion on AUXADC channel 1, measured during a transmission burst AUXADC1B 12-bit result of the A/D conversion on AUXADC channel 1, measured outside a transmission burst AUXADC2 AUXADC3 AUXADC4 12-bit result of the A/D conversion on AUXADC channel 2 12-bit result of the A/D conversion on AUXADC channel 3 12-bit result of the A/D conversion on AUXADC channel 4
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Baseband and audio interface for GSM
12.3.6 VOICE BAND CONTROL REGISTER
PCF50732
The Voice band control register is used to control the following functionality of the voice band CODEC: * Analog input source: microphone (MICAMP) or auxiliary (AUXMIC) input * Analog output device: earphone (EARAMP), auxiliary (AUXAMP) or buzzer (BUZAMP) output; this register allows individual control of all three output amplifiers * EARAMP output mode: single-ended (EARP) or differential (EARN/EARP). This selects the input source for the EARAMP-N amplifier. In single-ended mode EARAMP-N will be at Vref, in differential mode it will carry the output signal * General purpose output pin: AMPCTRL * Receive and transmit path delay values * ASI clock mode * TX gain boost (MICHI). Table 22 Voice band control register (address 1010 and subaddresses) X = don't care during a read/or write access. SUBADDRESS FUNCTION 11 (s2) 0 10 (s1) 0 9 (s0) 0 8 7 6 VALUE FUNCTION SETTING 5 4 3 2 1 0 0 MICAMP (default) 1 AUXMIC X X X Select output amplifier 0 0 1 don't care X X X 0 1 EARAMP output mode AMPCTRL pin polarity Receive path data channel Transmit path data channel ASI clock mode TX gain boost (MICHI) 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 don't care don't care don't care don't care don't care d d c c b b X X X X 0 1 X X X X 0 1 X X X X 0 EARAMP-P off 1 EARAMP-P on (default) X EARAMP-N off X EARAMP-N on (default) X AUXAMP off (default) X AUXAMP on X BUZAMP off (default) X BUZAMP on 0 single-ended 1 differential (default) 0 active LOW 1 active HIGH (default) a a 4-bit delay value (default = 0)
Select input source
don't care
0 single clock (default) 1 double clock 0 7 dB 1 35 dB (default)
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Baseband and audio interface for GSM
12.3.7 VOICE BAND VOLUME REGISTER
PCF50732
Voice band gain settings can be independently programmed for: TXPGA, RXPGA, RXVOL and SidePGA. Table 23 Voice band volume register (address 1011 and subaddresses) X = don't care during a read/or write access. SUBADDRESS FUNCTION TXPGA gain RXPGA gain RXVOL gain SidePGA gain Band gap setting level Experimental bits 11 10 9 (s2) (s1) (s0) 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 8 X X X X X X 7 X X X X X X 6 X X X X X 5 a a a a a VALUE 4 b b b b b pll 3 c c c c c dc 2 d d d d X 1 e e e e X 0 f f f f X SELECTED RANGE -24 to +12 dB -30 to +6 dB DEFAULT SETTING
0 dB -12 dB mute pll on, all others off
-100 to +75 mV 0 mV offset
X dir
vbch hclk bgb -
Table 24 Voice band volume registers value description VALUE TXPGA gain RXPGA gain RXVOL gain SidePGA gain Experimental bits REMARKS microphone calibration earphone calibration DESCRIPTION TXPGA and RXPGA settings use the 6-bit binary fixed point value `ab.cdef' as a multiplier for each PCM-sample. This results in a control range of +12 to -24 dB. See note 1a.
customer volume control RXVOL and SidePGA settings use the 6-bit binary fixed point value `a.bcdef' as a multiplier for each PCM-sample. This results - in a control range of +6 to -30 dB (and mute). See note 1b. - * dir: bypass clock buffer * pll: clock optimizer * dc: bypass clock capacitor * vbch: voice band chopping * hclk: 26 MHz master clock input * bgb: band gap boost
Band gap setting level Note
do not use
1. Possible gain settings are listed in Table 25 or can be calculated using the following formulae (`n' is an integer that represents the value that is written into the register; n = 0 to 63): n a) RXPGA and TXPGA: gain = 20 x log ----- ; add 6.02 dB to each gain for RXPGA and TXPGA settings. 16 n b) RXVOL and SidePGA: gain = 20 x log ----32
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30
Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
12.3.7.1 Possible gain selections for voice band blocks: RXPGA, TXPGA, RXVOL and SidePGA
PCF50732
Table 25 shows the possible gain selections for the voice band blocks RXPGA, TXPG, RXVOL and SidePGA. It should be noted that not all possible combinations of these volume settings are meaningful; setting RXPGA, SidePGA and RXVOL to maximum will result in clipping of the output signal. Table 25 Gain selections BINARY CODE 111111 111110 111101 111100 111011 111010 111001 111000 110111 110110 110101 110100 110011 110010 110001 110000 101111 101110 101101 101100 101011 101010 101001 101000 100111 100110 100101 100100 100011 100010 100001 100000 GAIN (dB) RXPGA/TXPGA 11.88 11.74 11.60 11.46 11.31 11.17 11.01 10.86 10.70 10.54 10.38 10.22 10.05 9.88 9.70 9.52 9.34 9.15 8.96 8.77 8.57 8.36 8.15 7.94 7.72 7.49 7.26 7.02 6.78 6.53 6.27 6.00 RXVOL/SidePGA 5.88 5.74 5.60 5.46 5.31 5.17 5.01 4.86 4.70 4.54 4.38 4.22 4.05 3.88 3.70 3.52 3.34 3.15 2.96 2.77 2.57 2.36 2.15 1.94 1.72 1.49 1.26 1.02 0.78 0.53 0.27 0.00 BINARY CODE 011111 011110 011101 011100 011011 011010 011001 011000 010111 010110 010101 010100 010011 010010 010001 010000 001111 001110 001101 001100 001011 001010 001001 001000 000111 000110 000101 000100 000011 000010 000001 000000 GAIN (dB) RXPGA/TXPGA 5.72 5.44 5.14 4.84 4.52 4.20 3.86 3.50 3.13 2.75 2.34 1.92 1.47 1.00 0.51 0.00 -0.58 -1.18 -1.82 -2.52 -3.28 -4.10 -5.02 -6.04 -7.20 -8.54 -10.12 -12.06 -14.56 -18.08 -24.10 off RXVOL/SidePGA -0.28 -0.56 -0.86 -1.16 -1.48 -1.80 -2.14 -2.50 -2.87 -3.25 -3.66 -4.08 -4.53 -5.00 -5.49 -6.02 -6.58 -7.18 -7.82 -8.52 -9.28 -10.10 -11.02 -12.04 -13.20 -14.54 -16.12 -18.06 -20.56 -24.08 -30.10 off
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Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
12.3.8 POWER CONTROL REGISTER
PCF50732
The Power control register is used to control power-up and power-down of the different sections of the device. Changing the power status is accomplished by addressing the device as shown in Table 26 and setting bit 0 (= a) according to the required state: a = 0 power-down a = 1 power-up. Setting the baseband RX or TX flag is functionally equivalent to setting RXON or TXON respectively (logical OR function). The CSI is also accessible when the band gap is powered down. Therefore no reset is required to power-up after total power-down. Table 26 Power control register (address 1100 and subaddresses) SUBADDRESS FUNCTION AUXDAC1 AUXDAC2 AUXDAC3 Voice band transmit Voice band receive Vref Baseband receive Baseband transmit Complete device 12.3.9 RAM INTERFACE REGISTER 11 10 9 8 (s3) (s2) (s1) (s0) 0 0 0 0 0 0 1 1 1 0 0 0 1 1 1 0 0 1 0 1 1 0 0 1 0 0 1 1 0 1 0 1 0 0 1 1 don't care 7 6 5 VALUE 4 3 2 1 0 a a a a a a a a a DEFAULT VALUE 0 1 0 0 0 1 0 0 1 STATUS off on off off off on off off on
The RAM interface register is a general purpose communication channel between the serial interface CSI and the voice band signal processor. None of the processor registers have default values. The Voice band control register is used to communicate with the voice band signal processor. Register functions with subaddress `00' to `11' can be used to program the Instruction RAM (IRAM) when the voice band processor is not running, i.e. when voice band receive and transmit sections are both powered down. The IRAM registers are used to write into the voice band instruction RAM.
Normal operation is to write an address into the VSP instruction RAM program counter and write low and high bytes of the 16-bit instructions into their respective locations. No auto-increment is foreseen, i.e. the address register must be updated by the user. Writing to the IRAM is only possible when voice band transmit and receive sections are both powered off. If this is not the case write actions are ignored. Reading back from the IRAM is not straightforward due to the need for an extra clock pulse when accessing RAMs; when reading back the contents of RAM locations 1, 2, 3 and 4 actual output is `undefined' as 1, 2, 3, etc.
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Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
Table 27 RAM interface register (address 1101 and subaddresses) X = don't care during a read/or write access. SUBADDRESS FUNCTION VSP instruction RAM data low-byte VSP instruction RAM data high-byte VSP instruction RAM program counter VSP interface register 12.3.10 BASEBAND RECEIVE CONTROL REGISTER 11 (s1) 0 0 1 1 10 (s0) 0 1 0 1 9 X X X x9 8 X X a8 x8 7 d7 d7 a7 x7 6 d6 d6 a6 x6 VALUE 5 d5 d5 a5 x5 4 d4 d4 a4 x4 3
PCF50732
2 d2 d2 a2 x2
1 d1 d1 a1 x1
0 d0 d0 a0 x0
d3 d3 a3 x3
Normal bandwidth refers to an input signal bandwidth of 100 kHz used for ZIF operation, double bandwidth is 200 kHz used for NZIF operation. Normal sampling refers to a sampling rate of 12MCLK, double sampling refers to sampling at MCLK. Table 28 Baseband receive control register (address 1110) VALUE FUNCTION 11 Normal bandwidth; normal sampling (ZIF) double sampling; note 2 Double bandwidth; normal sampling (NZIF) double sampling Notes 1. Default value. 2. Do not use this function. 0 0 0 0 don't care 1 1 0 1 542 kHz 271 kHz 0 0 0 0 don't care 0 0 0 1 271 kHz(1) 135 kHz 10 9 8 7 6 5 4 3 2 1 0 OUTPUT RATE
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Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
12.3.11 TEST MODE REGISTER
PCF50732
Only test mode 8 (TM8) is available to the end user. It is used to mark baseband-I (BB-I) samples with a logic 0 and baseband-Q (BB-Q) samples with a logic 1 on the LSB of the 12-bit value. Table 29 Test mode register (address 1111) TEST MODE NM TM1 TM2 TM3 TM4 TM5 TM6 TM7 TM8 TM9 TM10 TM11 TM12 VALUE FUNCTION 11 10 normal mode (default) baseband transmit (BBTX) I digital baseband receive (BBRX) digital voice band (VB) loop digital voice band transmit/receive (VBTX/RX) digital CSI baseband (BB) DACs voice band receive (VBRX) DAC current sources I/Q marking test voice band signal processor test mode VSP signature output mode MCLK input reflected on BDIO baseband bitstream output don't care 9 8 7 6 5 4 3 0 0 0 0 0 0 0 0 1 1 1 1 1 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0
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34
Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
13 VOICE BAND SIGNAL PROCESSOR (VSP) 13.1 Hardware description
PCF50732
The VSP used in the PCF50732 is a 30-bit fixed point VSP with separate data and instruction areas. The data path consists of two guard bits, 16 data bits before and 12 data bits behind the binary point for a total of 30 bits. Twos complement notation is used inside the data path. Intermediate results from calculations are stored in a 64 x 30-bit wide data RAM. Data and Programmable Gain Amplifier (PGA) settings are read in via 7 input ports and written back into 3 output ports. The instruction path uses a 16-bit format with the 4 MSBs designating the opcode and the trailing 12 bits used to describe the operand. The VSP has 12 major instructions; some instructions use two opcodes (operation codes). The addressing range is 9 bits wide, allowing for a total of 512 instructions, which is more than adequate for the filter types it is intended to calculate. Some room is available for Built-In Self Test (BIST). The ALU consists of a 30-bit subtractor, a 30-bit adder and a 30 x 16-bit `modified booth'-type parallel multiplier. The VSP's accumulator has built-in overrange checking and will limit values to their minimum (in case of underflow) or maximum (in case of overflow) value. The VSP engine is designed to operate at 4 MIPS on a 8 kHz PCM signal. All instructions take one clock-cycle to complete. It should be noted that since the noise shaper operates at a sample rate of 32 kHz and the voice band filter operates at a sample rate of 40 kHz it is necessary to transfer 4 samples to the receive output and to read 5 samples from transmit input for each frame.
No buffering is foreseen for these samples, which means that the VSP program is responsible for proper spacing in time of the input- and output samples. Failure to ensure proper spacing will result in heavily distorted signals. Synchronization to the 8 kHz frame-sync signals AFS is also done under program control. The VSP program must ensure that noise shaper and FIR filter are properly reset before actual operation is started. A VSP-emulator and a VSP-assembler have been written in order to facilitate program development. The assembler generates a stream of 16-bit words that need to be loaded into the instruction RAM. This is done by repeated writes to the VSP control register. The sequence would be as follows: 1. Write address into the VSP instruction RAM program counter register 2. Write the upper 8 bits into the VSP instruction RAM data high-byte register 3. Write the lower 8 bits into the VSP instruction RAM data low-byte register. This sequence should be repeated until the VSP is fully programmed. Programming can only be done when the VSP is not active. The VSP program counter will be set to location 0 and operation starts after enabling voice band transmit or voice band receive. See also the CSI description in Chapter 12.
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Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
PCF50732
handbook, full pagewidth
INPUT PORTS RAM/ROM 512 x 30-BIT (from ADI) (from FIR) CTE in (9.0) or (0.12)
(1)
RX in (16.0)
TX in (16.0)
CSI in
TXPGA (2.4)
RXPGA RXVOL SidePGA (2.4) (1.5) (1.5)
PC
(12.0)
INPUT SELECTOR (6.0) (18.12) FLAGS (2.0) RAM 64 x 30-BIT INDEX AFS ALU (18.12) ACCUMULATOR (18.12) (18.12)
(6.0)
OUTPUT REGISTER (16.0) RX out (16.0) TX out (12.0) CSI out
(to NOISE SHAPER)
(to ADO)
MGR998
OUTPUT PORTS
The program ROM and program counter are not shown. (1) (x.y) designates a x + y bits wide data stream with x bits before and y bits after the binary point.
Fig.12 Voice band Signal Processor (VSP) block diagram.
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Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
13.2 VSP assembler language
PCF50732
The stack for return addresses is only one entry deep which means that nesting of subroutines is not possible. Table 30 VSP instruction set X = don't care during a read/or write access. For the description of the bit symbols see notes 1 to 8. MNEMONIC LDA STO RTN ADD SUB MUL JMFS JMFC JSFS JSFC STF IDX Notes 1. c11 to c0 denotes a 12-bit twos complement coefficient between -1 and +1. 2. m3 to m0 denotes a 4-bit instruction mode descriptor. 3. f2 to f0 denotes a 3-bit flag descriptor. 4. a8 to a0 denotes a 9-bit address. 5. i5 to i0 denotes a 6-bit index register value. 6. a8 to a0 denotes a 9-bit address. 7. X is a don't care bit. 8. im2 to im0 denotes a 3-bit instruction mode descriptor for the IDX operator. INSTRUCTION Load accumulator Store accumulator Return from subroutine Add to accumulator Subtract from accumulator Multiply with accumulator Jump if flag set Jump if flag clear Jump subroutine if flag clear Set/clear flag Index operations I3 I2 I1 0 0 0 0 0 1 1 1 1 1 1 0 0 0 1 1 0 0 0 1 1 1 1 0 1 1 0 1 0 1 1 0 0 1 1 I0 m3 m3 0 1 m3 m3 m3 m3 m3 m3 0 1 0 1 0 1 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 c11 m2 m2 X c11 m2 c11 m2 c11 m2 f2 f2 f2 f2 f2 im2 c10 m1 m1 X c10 m1 c10 m1 c10 m1 f1 f1 f1 f1 f1 c9 m0 X c9 c9 c9 f0 f0 f0 f0 f0 c8 X X c8 c8 c8 c7 X X c7 c7 c7 c6 X X c6 c6 c6 c5 c4 c3 c2 c1 c0 m0 d8 d7 d6 d5 d4 d3 d2 d1 d0 d5 d4 d3 d2 d1 d0 X c5 c5 c5 X c4 c4 c4 X c3 c3 c3 X c2 c2 c2 X c1 c1 c1 X c0 c0 c0
m0 d8 d7 d6 d5 d4 d3 d2 d1 d0 m0 d8 d7 d6 d5 d4 d3 d2 d1 d0 m0 d8 d7 d6 d5 d4 d3 d2 d1 d0 a8 a7 a6 a5 a4 a3 a2 a1 a0 a8 a7 a6 a5 a4 a3 a2 a1 a0 a8 a7 a6 a5 a4 a3 a2 a1 a0 a8 a7 a6 a5 a4 a3 a2 a1 a0 X X X X X X X i5 X i4 X i3 X i2 X i1 d0 i0
Jump subroutine if flag set 1
im1 im0
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Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
Table 31 Mode descriptions m3 0 0 0 0 0 1 Note 1. Value range in increments of 1. Table 32 Index mode descriptions im2 0 0 1 im1 0 0 0 im0 0 1 0 NAME store increment accu index = d5 to d0 index = (d5 to d0) + index index = accu OPERAND m2 0 0 0 0 1 m1 0 0 1 1 0 m0 0 1 0 1 0 MODE NAME register register indexed port small integer index OPERAND R(d5 to d0) P(d2 to d0) d8 to d0 index RANGE register 0 to 63 ports 0 to 7 -256 to +255; note 1 0 to 63; note 1
PCF50732
ASSEMBLER SHORT HAND r i p s i c
R((d5 to d0) + index) register 0 to 63
bits 11 to 0 form a 12-bit twos complement coefficient between -1 and +1
Table 33 Flag descriptions f2 0 0 0 0 1 1 1 1 f1 0 0 1 1 0 0 1 1 f0 0 1 0 1 0 1 0 1 NAME ALW INZ EQ0 EQ1 SYNC A B C DESCRIPTION always set set if accu is all 0 set if accu is all 1 PCM sync signal user flag A user flag B user flag C used to reset noise shaper and FIR filter used to sync VSP to external PCM signal user REMARKS flag is clear in VSP test mode; used to initiate BIST TYPE system
set if index not zero used to implement loops
Table 34 Port descriptions P2 0 0 0 0 1 1 1 1 P1 0 0 1 1 0 0 1 1 P0 0 1 0 1 0 1 0 1 NAME Receive (RX) Transmit (TX) CSI ZERO TXPGA RXPGA RXVOL SidePGA DIRECTION read/write read/write read/write read read read read read RANGE -32768 to +32767 (16 bits) -32768 to +32767 (16 bits) -2048 to +2047 (12 bits) fixed 0 0 to 63 (-24 to +12 dB) 0 to 63 (-24 to +12 dB) 0 to 63 (-20 to +6 dB) 0 to 63 (-20 to +6 dB)
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Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
13.3 13.3.1 Descriptions of the VSP instruction set CONVENTIONS * f.l. = a 3-bit flag descriptor * addr = a 9-bit address
PCF50732
In the descriptions of the VSP instruction set: * A = the 30-bit accumulator * I = the 6-bit index register * r.a. = a 6-bit register address * p.n. = a 3-bit port number (address) * coeff = a 12-bit coefficient 13.3.2 LDA INSTRUCTION
* stack = a one entry deep return address stack * PC = a 9-bit program counter * o.a. = the 9-bit old address * s.i. = small integer * X = don't care during a read/or write access.
The LDA (Load accumulator) instruction is used to load data into the VSP's accumulator. Flags affected are EQ0 and EQ1. Table 35 LDA instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 coefficient 0XXX 1XXX 1 register address register address small integer X X X 2 1 0 OPERATION coeff A R(r.a.) A ASSEMBLER LDA r LDA p LDA s LDA x NAME load register load register indexed load port load integer load index
LDA c load coefficient
R(r.a. + I) A LDA i s.i. A IA
0 X X X X X X port number P(p.n.) A 0XXXXXX
13.3.3
STO INSTRUCTION
The STO (Store accumulator) instruction is used to store data into register RAM or output ports. No flags are affected. Table 36 STO instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 0XXX 1XXX 2 1 0 OPERATION A R(r.a.) ASSEMBLER STO r STO p NAME store register store register indexed store port
register address register address
A R(r.a. + I) STO i
0 X X X X X X port number A P(p.n.)
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Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
13.3.4 ADD INSTRUCTION
PCF50732
The ADD (Add to accumulator) instruction is used to add data to the VSP's accumulator. Flags affected are EQ0 and EQ1. Table 37 ADD instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 coefficient 0XXX 1XXX register address register address 2 1 0 OPERATION A + coeff A A + R(r.a.) A ASSEMBLER ADD r NAME add register add register indexed add port add integer add index
ADD c add coefficient
A + R(r.a. + I) A ADD i ADD p ADD s ADD x
0 X X X X X X port number A + P(p.n.) A 1 small integer X X X A + s.i. A A+IA 0XXXXXX
13.3.5
SUB INSTRUCTION
The SUB (Subtract from accumulator) instruction is used to subtract data from the VSP's accumulator. Flags affected are EQ0 and EQ1. Table 38 SUB instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 coefficient 0XXX 1XXX register address register address 2 1 0 OPERATION A - coeff A A - R(r.a.) A ASSEMBLER NAME
SUB c subtract coefficient SUB r subtract register subtract register indexed subtract port subtract integer subtract index
A - R(r.a. + I) A SUB i SUB p SUB s SUB x
0 X X X X X X port number A - P(p.n.) A 1 small integer X X X A - s.i. A A-IA 0XXXXXX
13.3.6
MUL INSTRUCTION
The MUL (Multiply with accumulator) instruction is used to multiply data with the VSP's accumulator. Flags affected are EQ0 and EQ1. The second operand of the multiplication is restricted to 16-bit; e.g. R(r.a.). Table 39 MUL instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 coefficient 0XXX 1XXX register address register address 2 1 0 OPERATION A x coeff A A x R(r.a.) A ASSEMBLER NAME
MUL c multiply coefficient MUL r multiply register multiply register indexed multiply port multiply integer multiply index
A x R(r.a. + I) A MUL i MUL p MUL s MUL x
0 X X X X X X port number A x P(p.n.) A 1 small integer X X X A x s.i. A AxIA 0XXXXXX
1999 May 03
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Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
13.3.7 JMFS INSTRUCTION
PCF50732
The JMFS (Jump if flag set) is used for conditional jumps. The jump is carried out when the flag is set, otherwise the PC is simply incremented. Table 40 JMFS instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 0 flag address OPERATION PC ASSEMBLER JMFS
13.3.8
JMFC INSTRUCTION
The JMFC (Jump if flag clear) is used for conditional jumps. The jump is carried out when the flag is clear, otherwise the PC is incremented. Table 41 JMFC instruction 15 1 13.3.9 14 0 13 1 12 1 11 10 flag 9 8 7 6 5 4 3 2 1 0 OPERATION PC ASSEMBLER JMFC
address
JSFS INSTRUCTION
The JSFS (Jump subroutine if flag set) is used for conditional call to a subroutine. The jump is carried out when the flag is set, otherwise the PC is incremented. Note that the return stack is just one entry deep, so nesting of subroutines is not allowed. Table 42 JSFS instruction 15 1 14 1 13 1 12 0 11 10 flag 9 8 7 6 5 4 3 2 1 0 OPERATION stack PC ASSEMBLER JSFS
address
13.3.10 JSFC INSTRUCTION The JSFC (Jump subroutine if flag clear) is used for conditional jumps to a subroutine. The jump is carried out when the flag is clear, otherwise the PC is incremented. It should be noted that the return stack is just one entry deep, so nesting of subroutines is not allowed. Table 43 JSFC instruction 15 1 14 1 13 1 12 1 11 10 flag 9 8 7 6 5 4 3 2 1 0 OPERATION stack PC ASSEMBLER JSFC
address
13.3.11 RTN INSTRUCTION The RTN (Return from subroutine) is used to return from a subroutine. Table 44 RTN instruction 15 0 14 0 13 1 12 1 11 X 10 X 9 X 8 X 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 X OPERATION stack PC RTN ASSEMBLER
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Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
13.3.12 STF INSTRUCTION
PCF50732
The STF (Set/clear flag) instruction is used to set or clear the user flags A, B or C. System flags cannot be set or reset under program control. Table 45 STF instruction 15 1 14 1 13 0 12 0 11 10 flag 9 8 X 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 value OPERATION ASSEMBLER STF
13.3.13 IDX INSTRUCTION The IDX (Index operations) instruction is used to store and increment/decrement index values. It should be noted that additions to the index register is done in modulo 64. A `decrement index register by one' could therefore be programmed as `IDX + 63'. The `IDX A' instruction loads the 6 bits to the left of the binary point into the index register, i.e. it stores the integer part modulo 64 into I. Table 46 IDX instruction 15 1 1 1 13.4 14 1 1 1 13 0 0 0 12 1 1 1 11 0 0 1 10 0 0 0 9 0 1 0 8 X X X 7 X X X 6 X X X X X 5 4 3 2 1 0 OPERATION I I + I X X AI ASSEMBLER IDX = IDX + IDX A
value value X X
The assembler/emulator
A 2-pass assembler and an emulator was made to assist with the development of VSP programs. The software programs are written in `C' and currently run under NT, HPUX and LINUX operating systems. The assembler reads assembler source files and produces a log file, sets of VHDL or Verilog stimuli and an output file containing CSI instructions that, when loaded, will load the executable into the VSP RAM. Requirements for the assembler source code are: * One instruction or pseudo instruction (see Table 47) per line * No empty lines * A maximum of 512 instructions * Operation always starts at instruction 0. Table 47 Assembler pseudo instructions MNEMONIC . label define include -INSTRUCTION {<.>< >} {< > < > {< >} {<-->< > DEFINITION Defines a location inside the source code. Is usually used as an argument to JMF/JSF instructions. Defines a variable and assigns a value to it. These variables can then be referenced in the assembler instructions. Reads in another source code file and then continues with the current file. Defines a comment; the rest of the line is skipped.
1999 May 03
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Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
14 LIMITING VALUES In accordance with Absolute Maximum Rating System (IEC 134). SYMBOL VDD IDD II1 II2 VI Ptot Tamb Tstg supply voltage supply current DC current into any pin; except EARP/EARN, AUXSP and BUZ DC current into pins EARP/EARN, AUXSP and BUZ input voltages on all inputs total power dissipation operating ambient temperature storage temperature PARAMETER - -10 -100 -0.5 - -40 -65 MIN. -0.5
PCF50732
MAX. +3.3 30 +10 +100 800 +85 +150 V
UNIT mA mA mA mW C C
VDD + 0.5 V
15 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 80 UNIT K/W
16 DC CHARACTERISTICS Tamb = -40 to +85 C; VSS = 0 V (ground pins must be interconnected externally); VDDA VDDD; VDDA(bb) = VDDA(vb) = VDDA(vbo) = VDDA(ref) = VDDA = 2.5 to 2.75 V (supply pins must be interconnected externally); all voltages with respect to VSS unless otherwise specified. SYMBOL Istb(tot) Pav PARAMETER total standby current average power consumption CONDITIONS - VDDD = 1.5 V; - VDDA = 2.7 V; without load on audio outputs EARP, EARN, AUXSP and BUZ MIN. TYP. 10 15 - - MAX. UNIT A mW
Digital power supply: VDDD VDDD VIL VIH ILI VOL VOH VOL VOH digital supply voltage 1.0 1.5 - - 1 - - - - 2.75 V
Digital inputs: CCLK, CEN, CDI, TXON, RXON, AUXST, ADI, AFS, ACLK and RESET LOW-level input voltage HIGH-level input voltage input leakage current 0.0 0.7VDDD - - 0.7VDDD - 0.7VDDD 0.3VDDD VDDD - V V A
Digital outputs: BIEN, BOEN, ADO and AMPCTRL LOW-level output voltage HIGH-level output voltage Isink = 1.5 mA Isource = 1.5 mA Isink = 1.5 mA Isource = 1.5 mA 0.2VDDD - V V
Digital output: BIOCLK LOW-level output voltage HIGH-level output voltage 0.2VDDD - V V
1999 May 03
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Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
PCF50732
SYMBOL
PARAMETER
CONDITIONS
MIN. - - 1 - - 1
TYP.
MAX.
UNIT
Digital bidirectional pins: CDO and BDIO VIL VIH ILI VOL VOH ILI LOW-level input voltage HIGH-level input voltage input leakage current LOW-level output voltage HIGH-level output voltage Isink = 1.5 mA Isource = 1.5 mA 0.0 0.7VDDD - - 0.7VDDD - 0.3VDDD VDDD - 0.2VDDD - - V V A V V A
Low-swing clock input: MCLK input leakage current
Analog power supplies: VDDA(bb), VDDA(vb), VDDA(vbo) and VDDA(ref) VDDA IDDA analog supply voltage analog supply current VDDD = 1.5 V; VDDA = 2.7 V; RXON active 2.5 - 2.7 3.5 2.75 - V mA
Analog reference pin: Vref Vref II(ref) Vbias(TXIQ) Vref(MIC) Vref(AUXMIC) Vbias(EAR) Vbias(AUX) Vbias(BUZ) DC reference level input source/sink current no external load - - 1.25 0.1 - - V A
Analog output pins: IP, IN, QP and QN DC bias level 1.175 - - - - - 1.25 1.325 - - - - - V
Analog input pins: MICP and MICN DC input reference level 0.5Vref 0.5Vref Vref Vref Vref V
Analog input pins: AUXMICP and AUXMICN DC input reference level V
Analog output pins: EARP and EARN DC bias level V
Analog output pin: AUXSP DC bias level V
Analog output pin: BUZ DC bias level V
1999 May 03
44
Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
17 AC CHARACTERISTICS VDDD = 1.0 to 2.75 V; VDDA = 2.5 to 2.75 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL fclk Ci tdLHO tdHLO Ci tdLHO tdHLO VMCLK MCLK tst(TXIQ) Ro(TXIQ) Ri(RXIQ) Ci(RXIQ) Ri(AUXADC) Ri(eq)(MIC) Ri(eq)(AUXMIC) Ro(EARAMP) Ro(AUXAMP) Ro(BUZ) Note 1. Input MCLK is internally AC coupled; the signal must not go below VSS or above VDDD. PARAMETER master clock frequency CONDITIONS - - - - - output load = 20 pF output load = 20 pF - - MIN. TYP. 13.0
PCF50732
MAX. - - - - - - -
UNIT MHz
Digital input pins: CCLK, CEN, CDI, TXON, RXON, AUXST, ADI, AFS, ACLK and RESET input capacitance 5.0 pF
Digital output pins: BIOCLK, BIEN, BOEN, ADO and AMPCTRL output rise time output fall delay output load = 10 pF output load = 10 pF 10 10 ns ns
Digital bidirectional pins: CDO and BDIO input capacitance output rise time output fall delay 5.0 10 10 - - pF ns ns
Low-swing clock input: MCLK input amplitude duty cycle note 1 0.1 40 - - 0.5VDDD 60 - - - - - V % s
Analog output pins: IP, IN, QP and QN output settling time output resistance output load = 10 pF // 10 k, to 1 LSB, for 0.8 to 2.2 V f < 100 kHz 9.6 105 - 5
Analog input pins: IP, IN, QP and QN input resistance input capacitance differential 200 - - k pF
Analog input pins: AUXADC1, AUXADC2, AUXADC3 and AUXADC4 input resistance 1 M
Analog input pins: MICP and MICN equivalent input resistance differential 200 220 320 - k
Analog input pin: AUXMICP and AUXMICN equivalent input resistance 200 220 - - - k
Analog output pins: EARP and EARN output resistance f = 1 kHz 0 1
Analog output pin: AUXSP output resistance f = 1 kHz 0 1
Analog output pin: BUZ output resistance f = 1 kHz 0 1
1999 May 03
45
Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
18 FUNCTIONAL CHARACTERISTICS 18.1 Baseband transmit (BSI to TXI/Q) VDDA = 2.5 to 2.75 V; Tamb = -40 to +85 C. SYMBOL RESTXIQ S/NTXIQ FSINTXIQ VO(TXIQ)(p-p) VDC(TXIQ) AMATTXIQ VOFSTXIQ FRESPTXIQ PARAMETER resolution of TX DACs signal-to-noise TX DACs input sampling frequency output signal amplitude (peak-to-peak value) output DC level output amplitude matching between I and Q TX paths differential DC offset voltage between IP/IN or QP/QN frequency response of random output signal note 1 note 1 f = 0 to 100 kHz f = 200 kHz f = 250 kHz f = 400 kHz f = 600 kHz f = 1200 kHz f > 1800 kHz MPEITXIQ AGDTXIQ GDLTXIQ GDMATTXIQ PMATTXIQ PTERMSTXIQ maximum phase effect instance absolute group delay group delay linearity note 2 note 1 note 1 CONDITIONS MIN. - - - 0.9 1.15 -1.75 -0.15 -4.5 -3 - - - - - - - - - - - - -
PCF50732
TYP. 10 55 1.0 1.25 - - - - - - - - - - 22 10 100 - 0.5 0.5 1.5
MAX. - - 1.1 1.35 +1.75 +0.15 +4.5 - -30 -33 -60 -70 -70 -70 - - - 40 - 0.8 3.0
UNIT bit dB kHz V V % dB mV dB dB dB dB dB dB dB s s ns ns deg deg deg
270.833 -
measured at full-scale; 10 kHz < f < 100 kHz; group delay matching of I and Q TX paths load: 10 pF // 10 k phase matching of I and Q TX paths RMS phase trajectory error note 1 random input pattern; notes 1 and 3
PTEPEAKTXIQ peak phase trajectory error Notes 1. Measured at full-scale; load: 10 pF // 10 k; f = 67 kHz.
2. Not tested. Defined between the rising edge of BIOCLK which latches a data bit at BDIO to its corresponding maximum phase change on the analog outputs ITX and QTX. 3. Not tested.
1999 May 03
46
Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
18.2 Baseband receive (RXI/Q to BSI) VDDA = 2.5 to 2.75 V; Tamb = -40 to +85 C; all values valid for ZIF and NZIF modes. SYMBOL RESRXIQ S/NRXIQ VICM(RXIQ) VIDM(RXIQ) FSINRXIQ PARAMETER resolution signal to noise ratio input common mode voltage input differential voltage input sampling frequency (IP + IN)/2; (QP + QN)/2; referred to VSS (IP - IN); (QP - QN) Baseband receive control register = 0X Baseband receive control register = 1X Baseband receive control register = 00 or 11 Baseband receive control register = 10 FRESPRXIQ frequency response Baseband receive control register = 0X; note 1 f = 0 to 70 kHz; VIDM(RXIQ) = 150 mV (p-p) f = 90 kHz; VIDM(RXIQ) = 150 mV (p-p) f = 100 kHz; VIDM(RXIQ) = 150 mV (p-p) f = 200 kHz; VIDM(RXIQ) = 150 mV (p-p) f > 220 kHz; VIDM(RXIQ) = 150 mV (p-p) Baseband receive control register = 1X; note 1 and 2 f = 0 to 140 kHz; VIDM(RXIQ) = 150 mV (p-p) f = 180 kHz; VIDM(RXIQ) = 150 mV (p-p) f = 200 kHz; VIDM(RXIQ) = 150 mV (p-p) f = 400 kHz; VIDM(RXIQ) = 150 mV (p-p) f > 440 kHz; VIDM(RXIQ) = 150 mV (p-p) DYNRXIQ dynamic signal range ZIF mode NZIF mode SINADRXIQ signal to noise and distortion ratio f = 20 Hz to 135 kHz f = 20 Hz to 270 kHz f = 20.0 kHz; VIDM(RXIQ) = 2 V (p-p) f = 67.7 kHz; VIDM(RXIQ) = 2 V (p-p) f = 20 kHz; VIDM(RXIQ) = 150 mV (p-p) f = 67.7 kHz; VIDM(RXIQ) = 150 mV (p-p) OPC PSRRRXIQ GERRRXIQ GMATRXIQ output code in BDIO power supply ripple rejection gain error gain matching error for maximum input amplitude applying a 100 mV (p-p)/217 Hz sine wave on top of the analog power supply referenced to maximum amplitude at maximum input level 60 60 40 - - - - - -6 -0.5 -3 - 68 68 - 65 40 40 -0.8 - - - - 0 -3.5 -5.5 - - -0.8 - - - - 0 -3.5 -5.5 - - CONDITIONS I and Q word length at BSI MIN. - - 1.0 -1.5 - - - -
PCF50732
TYP. 12 66 1.25 - 6.5 13
MAX. UNIT - - 1.5 1.5 - - bit dB V V MHz MHz kHz kHz dB dB dB dB dB
FSOUTRXIQ output sample rate
270.833 - 541.667 - +0.3 - - -35 -45
+0.3 - - -35 -45 - - - - - - - - +6 +0.5 +3 5
dB dB dB dB dB dB dB dB dB dB dB LSB dB % dB % ns
1440 70 - - - -
-0.25 - GDMATRXIQ group delay matching measured at full-scale; 10 kHz < f < 100 kHz; of I and Q RX paths output load = 10 pF // 10 k
+0.25 dB
1999 May 03
47
Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
PCF50732
SYMBOL OFFSRXIQ POSTRXIQ
PARAMETER offset error power-on settling time ZIF mode NZIF mode
CONDITIONS before compensation after compensation including decimation filter
MIN. -40 -5 - -
TYP.
MAX. UNIT +40 +5 mV mV
- - - -
52 26 23 11.5
- - - -
s s s s
FGDRXIQ
filter group delay ZIF mode NZIF mode
Notes 1. Reference level is full-scale input at 67 kHz. 2. This will not be tested.
1999 May 03
48
Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
18.3 Voice band transmit (microphone to ASI) VDDA = 2.5 to 2.75 V; Tamb = -40 to +85 C. SYMBOL RESMICADC FSINMICADC GRANTXPGA GSTPTXPGA GTOLVBTX FRESPVBTX PARAMETER resolution of ADC internal sampling frequency calibration gain range calibration gain step size gain tolerance of coder digital filter frequency response of implemented standard VSP software (version: vb5_all) out-of-band rejection see Table 25 at TXPGA = 0 dB f < 100 Hz 100 Hz < f < 200 Hz f = 300 Hz to 3.3 kHz f = 3.3 to 3.4 kHz f 4 kHz FREJVBTX f = 4.6 kHz f = 6 to 30 kHz Microphone/auxiliary signal path VIN(rms) NIDLE THD SINAD nominal input level (RMS value) idle noise level (pin ADO) signal-to-noise and distortion TXPGA = 0 dB, MICHI = 1 TXPGA = 0 dB, MICHI = 0 psophometrically weighted(1); Tamb = 25 C - - - - 30 40 45 45 40 30 25 - -35 -7 - - - - - - - - - - CONDITIONS
PCF50732
MIN. TYP. MAX. - - -24 - 13 - 1000 - 0 64 +12 - +1.0 -20 -10 +1 0 -20 - - - - -75 1 - - - - - - - 2
UNIT bit kHz dB steps dB dB dB dB dB dB dB dB
-1.5 - - - -1 - 40 45 - - - - 45 50
-1.5 -
dBm dBm dBm0p(2) % dB dB dB dB dB dB dB LSB
total harmonic distortion f = 1 kHz; PGA = -4 dB; ADO = +2 dBm0 ADO = 3 dBm0 ADO = 0 dBm0 ADO = -10 dBm0 ADO = -20 dBm0 ADO = -30 dBm0 ADO = -40 dBm0 ADO = -45 dBm0
PSCTVBTX
power supply crosstalk
applying a 100 mV (p-p)/217 Hz sine wave on top of the analog power supply
Audio Serial Interface (ASI) FASOUT FSYNCAFS PCM output bit rate PCM frame synchronization frequency at pin AFS 128 - - 8 2048 kbits/s - kHz
Notes 1. Psophometrical weighting: a frequency weighting curve described in "ITU recommendation O.41". 2. The unit dBm0p: 0 dBm0p is generally defined as -3.14 dBFS, where dBFS denotes dB full scale, i.e. a signal with an amplitude covering the complete range of digital values. The suffix `p' refers to psophometrical weighting.
1999 May 03
49
Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
18.4 Voice band receive (ASI to earphone) VDDA = 2.5 to 2.75 V; Tamb = -40 to +85 C SYMBOL RESEARDAC FSINEARDAC GRANVOL GSTPVOL GRANPGA GSTPPGA GTOLVBRX PARAMETER resolution of DAC internal sampling frequency gain step range gain step size calibration PGA range gain step size gain tolerance of decoder digital steps; see Table 25 digital steps; see Table 25 CONDITIONS - - -30 - -24 - -1 40 f = 0 to 100 Hz f = 300 to 3300 Hz f = 3300 to 3400 Hz f = 4000 Hz f = 4600 Hz f = 28.6 kHz Audio Serial Interface (ASI) FASIN FSYNCAFS PCM input bit rate PCM frame synchronization frequency at pin AFS 128 - - 8 - -1.0 -2.0 - 38 40 MIN. 13 1000 -12 64 - 64 - - - - - - - - TYP. - -
PCF50732
MAX.
UNIT bit kHz dB steps dB steps dB dB dB dB dB dB dB dB
+6 - +12 - +1 - -20 +1.0 +1.0 -18 - -
GMUTEVBRX mute attenuation of decoder FRESPVBRX digital filter frequency response of implemented standard VSP software (version: vb5_all) out-of-band rejection
FREJVBRX
2048 -
kbits/s kHz
Earphone output: EARP and EARN Vref(EAR) Vo(EAR)(p-p) Io(EAR)peak GAINEARVOL DC reference level output voltage (peak-to-peak value) output source/sink current nominal gain from ASI to EARP/EARN load: 16 differential load: 8 single-ended load: 8 single-ended GRANVOL = -12 dB; load 32 differential single-ended GRANSIDVOL total sidetone gain (from MICP/MICN to EARP/EARN) THDEAR IDLNEAR total harmonic distortion GRANEARVOL = -12 dB idle noise at EARP/EARN psophometrically GRANEARPGA = 0 dB weighted(1); -13 -19 +5 -12 -18 - -11 -17 +41 dB dB dB - - - - Vref 2 1.5 100 - - - - V V V mA
- -
- -
1 -72
% dBmp(2)
1999 May 03
50
Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
PCF50732
SYMBOL SINADEAR
PARAMETER signal-to-noise and distortion ratio from ASI to earphone
CONDITIONS psophometrically weighted(1) at 3 dBm0 input signal level at 0 dBm0 input signal level
MIN. 30 35 - - - - - - - -
TYP. - - - - - - - -
MAX.
UNIT dB dB dB dB dB dB dB dB
at -10 dBm output signal level 45 at -20 dBm output signal level 42 at -30 dBm output signal level 40 at -40 dBm output signal level 30 at -45 dBm output signal level 25 PSRREAR power supply ripple rejection at EARP/EARN applying a 100 mV (p-p)/217 Hz sine wave on top of the analog power supply 70
Auxiliary output: AUXSP Vref(AUXSP) Vo(AUXSP) DC reference level output voltage load: 16 with 47 F in series to ground load: 8 with 100 F in series to ground Io(AUXSP)peak GAINAUXSP output source/sink current nominal gain from ASI to AUXSP - - - Vref Vref 1 Vref 0.77 62.5 -18 - - - - -17 V V V mA dB
load: 16 with 47 F in series to - ground load: 16 with 47 F in series to ground; GRANVOL = -12 dB -19
Buzzer output: BUZ Vref(BUZ) Vo(BUZ) Io(BUZ)peak GAINBUZ Notes 1. Psophometrical weighting: a frequency weighting curve described in "ITU recommendation O.41". 2. The unit dBmp: 0 dBmp refers to a voltage of a signal of 1 mW across a 600 load. The suffix `p' refers to psophometrical weighting. DC reference level output voltage output source/sink current nominal gain from ASI to BUZ load: 8 with 100 F in series to ground load: 8 with 100 F in series to ground; GRANVOL = -12 dB - - - -19 Vref 100 -18 - - -17 V V mA dB Vref - 0.77 -
1999 May 03
51
Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
18.5 Auxiliary digital-to-analog converters VDDA = 2.5 to 2.75 V; Tamb = -40 to +85 C. SYMBOL AUXDAC1 RESDAC1 VOMINDAC1 VOMAXDAC1 VDEFDAC1 MONDAC1 INLDAC1 DNLDAC1 OFFSDAC1 FSSTDAC1 LSBSTDAC1 AUXDAC2 RESDAC2 VOMINDAC2 VOMAXDAC2 VDEFDAC2 MONDAC2 INLDAC2 DNLDAC2 OFFSDAC2 FSSTDAC2 LSBSTDAC2 POSTDAC2 AUXDAC3 RESDAC3 VOMINDAC3 VOMAXDAC3 MONDAC3 INLDAC3 DNLDAC3 OFFSDAC3 FSSTDAC3 LSBSTDAC3 SSCDAC3 Notes resolution minimum output voltage maximum output voltage monotonicity range integral non-linearity(1) differential offset error full-scale settling time one LSB settling time output source/sink current non-linearity(2) register value: 000H register value: 3FFH - 0 2.1 - -5.0 -1.0 -40 load: 50 pF // 1 k, to VSS; 1 see Fig.13c - - 10 - 2.2 10 - - - 10 2.5 - - resolution minimum output voltage maximum output voltage output voltage after reset monotonicity range integral non-linearity(1) differential non-linearity(2) offset error full-scale settling time one LSB settling time power-on settling time load: 50 pF // 10 k, to VSS; see Fig.13b see Section 18.1 register value: 000H register value: FFFH register value: 800H - 0 2.1 - - - -1.0 -25 - - - 12 - 2.2 1.1 12 10 - - 40 8 - - resolution minimum output voltage maximum output voltage output voltage after reset monotonicity range integral non-linearity(1) non-linearity(2) differential offset error full-scale settling time one LSB settling time register value: 000H register value: 0FFH register value: 085H - 0 2.1 - - -5.0 -1.0 -80 load: 50 pF // 2 k, to VSS; - see Fig.13a - 8 - 2.2 1.147 8 - - - 40 8 - PARAMETER CONDITIONS MIN. TYP.
PCF50732
MAX.
UNIT
bit V V V bit LSB LSB mV s s
0.15 2.3 - - +5.0 +1.0 +80 - -
bit V V V bit LSB LSB mV s s ms
0.15 2.32 - - - +2.0 +25 - - 4
bit V V bit LSB LSB mV s s mA
0.15 2.3 - +5.0 +1.0 +40 15 - 2.5
1. INL: the difference of the output to the best fit line. INL(i) = [V(i) - (a + i x b)]/1 LSB; INL = (INL(i)(max) - INL(i)(min))/2. 2. DNL is the difference between individual code width and average code width (1 LSB); maximum and minimum specified. DNL(i) = [(V(i + 1) - V(i) - 1 LSB)/1 LSB]; DNL(min) > -1 is equivalent to monotonicity V(i + 1) > V(i). 1999 May 03 52
Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
18.6 Auxiliary analog-to-digital converters: AUXADC1, AUXADC2, AUXADC3 and AUXADC4 VDDA = 2.5 to 2.75 V; Tamb = -40 to +85 C. SYMBOL RESAUXADC VINAUXADC VINAUXADCMIN VINAUXADCMAX Ri(AUXADC) INLAUXADC DNLAUXADC GERRAUXADC OFFSAUXADC POSTAUXADC PARAMETER resolution input voltage Vin for output code 0 Vin for output code +1820 input resistance integral non-linearity differential non-linearity gain error offset error after compensation power-on settling time Vi = Vref after offset compensation CONDITIONS coded in 12 bits MIN. - 0.0 -20 - - - - -0.5 -3 - TYP. 1440 - - 2.0 1.0 2.5 2.5 - - 170
PCF50732
MAX. - 2.0 20 - - - - + 0.5 3 -
UNIT LSB V mV V M mV mV dB LSB s
18.7 Typical total current consumption The typical total current consumption values for the chip in different modes; Tamb = 25 C. TOTAL CURRENT (mA) ACTIVITY NOTE 1 Baseband transmit receive Voice band transmit and receive Voice band transmit and receive baseband transmit baseband receive Auxiliary ADC function Auxiliary DAC1 Auxiliary DAC2 Auxiliary DAC3 Idle with MCLK running Idle no MCLK; references on Idle Notes 1. VDDD = 2.3 V; VDDA = 2.65 V; external interface current is not included. 2. VDDD = 2.6 V; VDDA = 2.65 V; external interface current is not included. 3. For a signal at the earpiece differential output of amplitude `A' across a load resistance of `R', the current `I' must be 4A added, where: I = -- --- . -R 1999 May 03 53 7.32 8.52 2.75 2.35 1.55 4.35 0.23 0.18 0.01 7.51 8.91 2.86 2.49 1.59 4.56 0.24 0.19 0.01 voice band transmit and receive + baseband transmit + references + 13 MHz + CSI + auxiliary DACs 2 and 3 voice band transmit and receive + baseband receive + references + 13 MHz + auxiliary DAC 2 auxiliary ADC + CSI + references + 13 MHz + auxiliary DAC2 auxiliary DACs 1 and 2 + references + 13 MHz auxiliary DAC2 + references + 13 MHz auxiliary DACs 3 and 2 + CSI + baseband transmit + references + 13 MHz references + 13 MHz clock references; see Section 19.1.1 "Possibility 1" all blocks in power-down, no 13 MHz clock 3.96 5.14 4.79 4.04 5.41 4.94 baseband transmit + references + MCLK + BSI baseband receive + references + MCLK + BSI voice band transmit and receive + references + 13 MHz + auxiliary DAC2; note 3 NOTE 2 REMARKS
Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
18.8 Typical output loads
PCF50732
Figure 13 illustrates the typical loads for the outputs: AUXDAC1, AUXDAC2, AUXDAC3, EARP, EARN, AUXSP and BUZ.
handbook, halfpage
AUXDAC1 50 pF VSSA
MBL023
handbook, halfpage
AUXDAC2 50 pF VSSA
MBL024
2 k
10 k
a. AUXDAC1.
handbook, halfpage handbook, halfpage
b. AUXDAC2.
EARP or AUXSP
AUXDAC3 50 pF VSSA
MBH602
800 H 100 pF 16
1 k EARN
MBL020
c. AUXDAC3.
ndbook, halfpage
d. EARP/EARN or AUXSP.
handbook, halfpage
AUXSP or BUZ
8
AUXSP or BUZ
16
100 F VSS
MGS172 MBL021
47 F
VSS
e. AUXSP or BUZ; R = 8 .
f. AUXSP or BUZ; R = 16 .
Fig.13 Typical output loads.
1999 May 03
54
Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
19 APPLICATION INFORMATION
PCF50732
handbook, full pagewidth
G14
RFCLK
BUS
RFDO G11 RFDI G13 RFE_N1 F13 RFE_N2 F11
VDDD 68 nF
VDDA 68 nF
VDDA(vbo) 68 nF CLOCK DATA 17 16 18 IA IB QA QB 7 8 9 10
RFSIG[x]
AUXST 13 CCLK CDI CEN CDO 9 11 10 12
7
25 34 37
47
EN IP IN QP QN AUXDAC1 AUXDAC2 AUXDAC3 AUXADC1 AUXADC2 AUXADC3 AUXADC4
21 22 23 24
OM5178
PCF5087X
H13 J13 J11 H14 SIOXCLK SOXEN_N SIOXD SIXEN_N BIOCLK BIEN BDIO BOEN 15 16 17 18
27 28 29
13 MHz ON VCXO 13 MHz PA-CONTROL CIRCUITRY CHARGER BATTERY VOLTAGE BATTERY TEMPERATURE AMBIENT TEMPERATURE BATTERY TYPE microphone supply
RFSIG[y] RFSIG[z]
TXON RXON
19 20
31 32 33
EXTERNAL IOM2 B11 A11 D11 B10 FSC DCL DU DD AFS ACLK ADO ADI AMPCTRL L7 K14 K12 RSTO_N system reset 68 nF RST_N RESET Vref 5 36 8 CKI MCLK 3 4 1 2 14 6
PCF50732
30
38 39
AUXMICP AUXMICN
41 40 46
MICP
microphone supply
MICN EARP
45 44 43
EARN AUXSP BUZ
26 35 42 48
MGS173
(1) 10 nF can be used instead of 100 nF for high-pass filtering.
Fig.14 Application diagram.
1999 May 03
55
Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
19.1 Wake-up procedure from Sleep mode
PCF50732
Apart from being the status control signal of AUXDAC1, AUXDAC2 and the MCLK input, AUXST also starts a down-counter at each rising edge which controls the output drive capability of pin Vref. This is important for the following considerations. For current consumption reduction during Sleep mode there are two possibilities as shown in Section 19.1.1 and 19.1.2. 19.1.1 POSSIBILITY 1
A down-counter increases the band gap output drive capability for 32768 MCLK cycles which equals approximately 2.5 ms. After that time the voltage at Vref has reached 0.5 mV of its final value. The timing diagram illustrates the situation (see Fig.15). Other points to note for this possibility: * As long as VDDD is not switched off, all registers keep their values. * As long as VDDA(bb) is not stable, the internal master clock is not running, because the first stage of the clock generator is supplied by VDDA. * All digital signals MUST remain stable for tMCLK after AUXST has gone HIGH. This is necessary to avoid any timing violations in the digital part of the PCF50732 caused by an unstable MCLK clock input. * The previously mentioned 2.5 ms for tBG are only valid for CVref = 68 nF 10% or less. The maximum of value 68 nF is highly recommended for good noise and power supply rejection figures.
Program every block into power-down via CSI except for the band gap, then pull AUXST LOW to switch off the clock internally. This results in a IDD(total) = 60 A (typical). Since the band gap hasn't been programmed into power-down, the only active reference is Vref. After a rising edge of AUXST, POSTDAC is in the order of 1.5 ms. 19.1.2 POSSIBILITY 2
If AUXST is also used to switch off the analog power supply, all references are shut down. The power-up time in this case is measured from the point where the MCLK clock input has valid levels or VDDA has settled to its final value (the latter of the two signals sets the reference point).
handbook, full pagewidth
t MCLK t VDD t BG (2.5 ms)
POSTDAC (4 ms)
VDDA
Vref
MCLK
AUXST AUXDAC1/ AUXDAC2
MGR999
tVDD: settling time until VDDA(bb) has reached 95% of its final value. It is assumed that tMCLK > tVDD; otherwise tBG and POSTDAC are related to tVDD. tMCLK: settling time until MCLK clock has reached at least 100 mV (peak-to-peak) level and a frequency of 13 MHz 10 kHz. tBG: settling time until voltage at Vref has reached 0.5 mV of its final value for CVref = 68 nF 10%. POSTDAC: settling time until AUXDAC1 and AUXDAC2 has reached the previously programmed value 2 LSBs.
Fig.15 Possible timing of wake-up sequence.
1999 May 03
56
Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
19.2 Microphone input connection and test set-up
PCF50732
handbook, halfpage
microphone supply 2 k
handbook, halfpage
MICP 100 nF (1)
MICP 100 nF
MICN 100 nF (1) 2 k
MBL022
MICN 100 nF
MGS171
(1) 10 nF can be used instead of 100 nF for high-pass filtering.
a. Microphone input connection.
b. Microphone input test set-up.
Fig.16 Microphone input connection and test set-up.
1999 May 03
57
Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
20 PACKAGE OUTLINE LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
PCF50732
SOT313-2
c
y X
36 37
25 24 ZE
A
e
E HE
A A2
A1
(A 3) Lp L detail X
wM pin 1 index 48 1 12 ZD bp D HD wM B vM B vM A 13 bp
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.60 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 7.1 6.9 E (1) 7.1 6.9 e 0.5 HD 9.15 8.85 HE 9.15 8.85 L 1.0 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 0.95 0.55 0.95 0.55 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT313-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 94-12-19 97-08-01
1999 May 03
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Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
21 SOLDERING 21.1 Introduction to soldering surface mount packages
PCF50732
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 21.4 Manual soldering
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. 21.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. 21.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed.
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1999 May 03
59
Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
21.5 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, SQFP PLCC(3), SO, SOJ not suitable suitable(2) suitable not recommended(3)(4) not recommended(5) suitable suitable suitable suitable suitable HLQFP, HSQFP, HSOP, HTSSOP, SMS not LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes
PCF50732
REFLOW(1)
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 22 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 23 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
1999 May 03
60
Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
NOTES
PCF50732
1999 May 03
61
Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
NOTES
PCF50732
1999 May 03
62
Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
NOTES
PCF50732
1999 May 03
63
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1999
Internet: http://www.semiconductors.philips.com
SCA63
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
465008/00/01/pp64
Date of release: 1999 May 03
Document order number:
9397 750 04998

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